MT48LC16M16LFFG Micron Technology Inc, MT48LC16M16LFFG Datasheet - Page 30

• Manufacturer Part Number: MT48LC16M16LFFG
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16LFFG

• Lead Free Status / Rohs Status: Not Compliant

TRUTH TABLE 2 – CKE
(Notes: 1-4)
256Mb: x16 Mobile SDRAM
MobileRamY26L_B.p65 – Pub. 04/03
NOTE: 1. CKE
CKE
H
H
L
L
n-1
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
8. Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on
CKE
that
or NOP commands should be issued on any clock edges occurring during the
commands must be provided during
edge n + 1.
traditional SDRAM components. For Mobile SDRAM devices, this command sequence is assigned to Deep Power Down.
H
H
L
L
n
n
t
is the logic state of CKE at clock edge n; CKE
CKS is met).
Reading or Writing
Deep Power-Down
CURRENT STATE
Clock Suspend
Clock Suspend
n
All Banks Idle
All Banks Idle
Power-Down
All Banks Idle
Power-Down
is the command registered at clock edge n, and ACTION
Self Refresh
Self Refresh
t
XSR period.
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
DEEP POWER DOWN
See Truth Table 3
AUTO REFRESH
COMMAND
VALID
n-1
X
X
X
X
X
was the state of CKE at the previous clock edge.
30
n
n
is a result of COMMAND
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Exit Deep Power-Down
ACTION
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Deep Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
t
XSR period. A minimum of two NOP
n
t
XSR is met. COMMAND INHIBIT
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
n
.
256Mb: x16
PRELIMINARY
NOTES
5
8
6
7
8