XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 143
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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- XC4VFX12-10FFG668C PDF datasheet
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Block RAM Applications
Block RAM Timing Model
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Instantiation of Additional Block RAM Primitives
Creating Larger RAM Structures
R
Table 4-7
Table 4-7: Single-Port Block RAM Primitives
The RAM_Ax templates (with x = 1, 2, 4, 9, 18, or 36) are single-port modules and
instantiate the corresponding RAMB16_Sx module.
RAM_Ax_By templates (with x = 1, 2, 4, 9, 18, or 36 and y = = 1, 2, 4, 9, 18, or 36) are dual-
port modules and instantiate the corresponding RAMB16_Sx_Sy module.
Block RAM columns have special routing to create wider/deeper blocks with minimal
routing delays. Wider or deeper RAM structures are achieved with a smaller timing
penalty than is encountered when using normal routing resources.
The CORE Generator software offers the designer an easy way to generate wider and
deeper memory structures using multiple block RAM instances. This program outputs
VHDL or Verilog instantiation templates and simulation models, along with an EDIF file
for inclusion in a design.
This section describes the timing parameters associated with the block RAM in Virtex-4
devices (illustrated in
Data Sheet
for reference.
RAMB16_S1
RAMB16_S2
RAMB16_S4
RAMB16_S9
RAMB16_S18
RAMB16_S36
lists all of the available single-port primitives for synthesis and simulation.
and the Timing Analyzer (TRCE) report from Xilinx software are also available
Primitive
Figure
www.xilinx.com
4-12). The switching characteristics section in the
Port Width
(16+2)
(32+4)
(8+1)
1
2
4
Block RAM Applications
Virtex-4
143
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