XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 231

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog Template
// Module: MUX_16_1_SUBM
//
// Description: Multiplexer 16:1
// Device: Virtex-4 Family
//-------------------------------------------------------------------
//
module MUX_16_1_SUBM (DATA_I, SELECT_I, DATA_O);
input [15:0]DATA_I;
input [3:0]SELECT_I;
output DATA_O;
wire [2:0]SELECT;
reg DATA_LSB;
reg DATA_MSB;
assign SELECT[2:0] = SELECT_I[2:0];
always @ (SELECT or DATA_I)
always @ (SELECT or DATA_I)
// MUXF7 instantiation
MUXF7 U_MUXF7
endmodule
//
*/
3'b001 : DATA_LSB <= DATA_I[1];
3'b010 : DATA_LSB <= DATA_I[2];
3'b011 : DATA_LSB <= DATA_I[3];
3'b101 : DATA_LSB <= DATA_I[5];
3'b110 : DATA_LSB <= DATA_I[6];
3'b111 : DATA_LSB <= DATA_I[7];
default : DATA_LSB <= 1'bx;
3'b001 : DATA_MSB <= DATA_I[9];
3'b010 : DATA_MSB <= DATA_I[10];
3'b011 : DATA_MSB <= DATA_I[11];
3'b101 : DATA_MSB <= DATA_I[13];
3'b110 : DATA_MSB <= DATA_I[14];
3'b111 : DATA_MSB <= DATA_I[15];
default : DATA_MSB <= 1'bx;
case (SELECT)
endcase
case (SELECT)
endcase
.I1(DATA_MSB),
.S(SELECT_I[3]),
.O(DATA_O)
);
3'b000 : DATA_LSB <= DATA_I[0];
3'b100 : DATA_LSB <= DATA_I[4];
3'b000 : DATA_MSB <= DATA_I[8];
3'b100 : DATA_MSB <= DATA_I[12];
(.I0(DATA_LSB),
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Multiplexer Primitives and Verilog/VHDL Examples
231