XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 395

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Timing Characteristics of 2:1 SDR Serialization
Timing Characteristics of 8:1 DDR Serialization
In
Clock Event 1
On the rising edge of CLKDIV, the word AB is driven from the FPGA fabric to the D1 and
D2 inputs of the OSERDES (after some propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word AB is sampled into the OSERDES from the D1 and
D2 inputs.
Clock Event 3
The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDES. This
latency is consistent with
SDR mode is one CLK cycle.
In
2:1 SDR example, a second OSERDES is required to achieve a serialization of 8:1. The two
OSERDES are connected and configured using the methods of section
Expansion,” page
while the remaining two bits are connected to D3–D4 of the slave OSERDES.
Clock Event 1
On the rising edge of CLKDIV, the word ABCDEFGH is driven from the FPGA fabric to the
D1–D6 inputs of the master OSERDES and D3–D4 of the slave OSERDES (after some
propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word ABCDEFGH is sampled into the master and slave
OSERDES from the D1–D6 and D3–D4 inputs, respectively.
Figure
Figure
CLKDIV
CLK
OQ
D1
D2
Event 1
8-18, the timing of a 2:1 SDR data serialization is illustrated.
8-19, the timing of an 8:1 DDR data serialization is illustrated. In contrast to the
Figure 8-18: OSERDES Data Flow and Latency in 2:1 SDR Mode
Clock
392. Six of the eight bits are connected to D1–D6 of the master OSERDES,
Event 2
Clock
Table
www.xilinx.com
B
A
8-11, which states that the latency of an OSERDES in 2:1
Output Parallel-to-Serial Logic Resources (OSERDES)
Clock
Event 3
A
C
D
B
C
E
F
D
E
F
“OSERDES Width
UG070_c8_25_041007
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