XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 202

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 5: Configurable Logic Blocks (CLBs)
202
SELECT[0]
SELECT[1]
SELECT[2]
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
Fast Lookahead Carry Logic
LUT
LUT
LUT
LUT
Wide-Input Multiplexer Summary
Each LUT can implement a 2:1 multiplexer. In each slice, the MUXF5 and two LUTs can
implement a 4:1 multiplexer. The MUXF6 and two slices can implement a 8:1 multiplexer.
The MUXF7 and the four slices of any CLB can implement a 16:1, and the MUXF8 and two
CLBs can implement a 32:1 multiplexer.
wide-input multiplexer. The section
the wide-input multiplexers.
Dedicated carry logic provides fast arithmetic addition and subtraction. The Virtex-4
FPGA CLB has two separate carry chains, as shown in the
8:1 MUX
Figure 5-18: 8:1 and 16:1 Multiplexers
F5
F5
F6
www.xilinx.com
8:1 Output
S2
S0
SELECT[2:0]
DATA[15:8]
SELECT[3]
DATA[7:0]
“Multiplexer Verilog/VHDL Examples”
Figure 5-18
summarizes the implementation of a
(S1 & S3)
(S0 & S2)
8:1
8:1
16:1 MUX
Figure
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
5-19.
F7
UG070_5_18_071504
has code for
16:1 output
CLB
R