XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 295

IC FPGA VIRTEX-4 FX 20K 672-FBGA

XC4VFX20-10FFG672C

Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX20-10FFG672C

Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
ADVANTEK
Quantity:
314
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX
Quantity:
1 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX
0
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Part Number:
XC4VFX20-10FFG672C
0
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Transmitter Termination
Receiver Termination
The Virtex-4 FPGA LVDS transmitter does not require any external termination.
lists the allowed attributes corresponding to the Virtex-4 FPGA LVDS current-mode
drivers. Virtex-4 FPGA LVDS current-mode drivers are a true current source and produce
the proper (EIA/TIA compliant) LVDS signal.
LVDS_25_DCI, LVDSEXT_25_DCI Usage
LVDS_25_DCI and LVDSEXT_25_DCI provide split termination for the P and N inputs
only. VRP and VRN should connect to 50Ω resistors.
Equivalently, it provides 100Ω differential impedance between the LVDS inputs.
Figure 6-73
on a board with 50Ω transmission lines.
External Termination
DCI
LVDS_25
LVDS_25
and
Figure 6-74
Figure 6-74: LVDS_25_DCI Receiver Termination
Figure 6-73: LVDS_25 Receiver Termination
IOB
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
IOB
www.xilinx.com
are examples of differential termination for an LVDS receiver
R DIFF = 2Z 0 = 100Ω
Z 0
Z 0
Z 0
Z 0
IOB
V
V
CCO
CCO
2R
2R
2R
2R
= 2.5V
= 2.5V
VRP
VRN
VRP
VRN
IOB
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
+
LVDS_25
LVDS_25_DCI
ug070_6_71_071904
+
ug070_6_72_071904
Table 6-33
295

Related parts for XC4VFX20-10FFG672C