XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 375

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
ISERDES Width Expansion
R
Figure 8-7
CLKDIV). No phase relationship between CLK and OCLK is expected. Calibration must be
performed for reliable data transfer from CLK to OCLK domain. See section
Clock for Strobe-Based Memory Interfaces – OCLK”
transferring data between CLK and OCLK.
Two ISERDES modules are used to build a serial-to-parallel converter larger than 1:6. In
every I/O tile (see
master and one slave. By connecting the SHIFTOUT ports of the master ISERDES to the
SHIFTIN ports of the slave ISERDES the serial-to-parallel converter can be expanded to up
to 1:10 (DDR) and 1:8 (SDR).
Figure 8-8
master and slave ISERDES modules. Ports Q3–Q6 are used for the last four bits of the
parallel interface on the slave ISERDES (LSB to MSB).
If the input is differential, the master ISERDES must be on the positive side of the
differential input pair. If the input is not differential, the input buffer associated with the
slave ISERDES is not available for use.
Data Input
Clock
Input
results in the correct hardware connection (phase-aligned inputs to CLK and
illustrates a block diagram of a 1:10 DDR serial-to-parallel converter using the
Figure 8-7: Clocking Arrangement Using BUFIO and BUFR
Figure 8-8: Block Diagram of ISERDES Width Expansion
“I/O Tile Overview” in Chapter
SERDES_MODE=MASTER
D
D
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
www.xilinx.com
SHIFTIN1
BUFIO
ISERDES
ISERDES
(Master)
(Slave)
Input Serial-to-Parallel Logic Resources (ISERDES)
SHIFTIN2
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q3
Q4
Q5
Q6
BUFR ( ÷ X)
6) there are two ISERDES modules; one
for more information about
Data_internal [0:5]
Data_internal [6:9]
CLKDIV
CLK
ISERDES
UG070_c8_23_032507
ug070_8_03_072604
“High-Speed
375