XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 385
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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- XC4VFX12-10FFG668C PDF datasheet
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
.
Clock Event 1
The entire first word CDAB has been sampled into the input side registers of the ISERDES.
The Bitslip pin is not asserted, so the word propagates through the ISERDES without any
realignment.
Clock Event 2
The second word CDAB has been sampled into the input side registers of the ISERDES.
The Bitslip pin is asserted, which causes the Bitslip controller to shift all bits internally by
1 bit to the right.
Clock Event 3
The third word CDAB has been sampled into the input side registers of the ISERDES. The
Bitslip pin is asserted for a second time, which causes the Bitslip controller to shift all bits
internally by three bits to the left.
On this same edge of CLKDIV, the first word sampled is presented to Q1–Q4 without any
realignment. The actual bits from the input stream that appear at the Q1–Q4 outputs
during this cycle are shown in A of
BITSLIP
CLKDIV
Q4–Q1
A
B
C
CLK
Q1–Q4 During Clock Event 3
(No Bitslip)
Q1–Q4 During Clock Event 4
(1st Bitslip, Rotate 1 Bit to Right)
Q1–Q4 During Clock Event 5
(2nd Bitslip, Rotate 3 Bits to Left)
D
Figure 8-13: Bits from Data Input Stream (D) of
C D A B C D
Figure 8-12: Bitslip Timing Diagram
www.xilinx.com
Event 1
Clock
Input Serial-to-Parallel Logic Resources (ISERDES)
Figure
Bitslip1
A B C D A B
8-13.
Event 2
Clock
C D A B C D
C D A B C D
C D A B C D
Bitslip2
CDAB
Event 3
Clock
C D
A B C D A B
A B C D A B
A B C D A B
BCDA
Event 4
Figure 8-12
Clock
UG070_c8_18_040207
UG070_8_09_032507
ABCD
Event 5
Clock
C D
C D
C D
385
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