XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 327

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Input DDR Primitive (IDDR)
R
Figure 7-8
signals.
primitive.
Table 7-3: IDDR Port Signals
Table 7-4: IDDR Attributes
Q1 and Q2
C
CE
D
R
S
DDR_CLK_EDGE
INIT_Q1
INIT_Q2
SRTYPE
Attribute Name
Name
Port
Table 7-4
shows the block diagram of the IDDR primitive.
Data outputs
Clock input port
Clock enable port
Data input (DDR)
Reset
Set
describes the various attributes available and default values for the IDDR
Function
Sets the IDDR mode of operation
with respect to clock edge
Sets the initial value for Q1 port
Sets the initial value for Q2 port
Set/Reset type with respect to
clock (C)
Figure 7-8: IDDR Primitive Block Diagram
www.xilinx.com
CE
D
C
Description
IDDR register outputs. Q1 is rising edge data, Q2 is
falling edge data.
The C pin represents the clock input pin.
The enable pin affects the loading of data into the DDR
flip-flop. When Low, clock transitions are ignored and
new data is not loaded into the DDR flip-flop. CE must
be High to load new data into the DDR flip-flop.
IDDR register input from IOB.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted
High.
R
S
IDDR
ug070_7_08_071404
Q1
Q2
Description
OPPOSITE_EDGE (default),
SAME_EDGE,
SAME_EDGE_PIPELINED
0 (default), 1
0 (default), 1
ASYNC, SYNC (default)
Table 7-3
Possible Values
lists the IDDR port
ILOGIC Resources
327