XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 341
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Quantity:
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
IDELAYCTRL Overview
R
IDELAYCTRL Primitive
IDELAYCTRL Ports
If the IDELAY or ISERDES primitive is instantiated with the IOBDELAY_TYPE attribute
set to FIXED or VARIABLE, the IDELAYCTRL module must be instantiated. The
IDELAYCTRL module continuously calibrates the individual delay elements (IDELAY) in
its region (see
temperature variations. The IDELAYCTRL module calibrates IDELAY using the user
supplied REFCLK.
Figure 7-13
RST - Reset
The reset input pin (RST) is an active-High asynchronous reset. IDELAYCTRL must be
reset after configuration (and the REFCLK signal has stabilized) to ensure proper IDELAY
operation. A reset pulse width T
after configuration.
IDELAY U1
//Set IOBDELAY_TYPE attribute to VARIABLE for Variable Delay Mode
//synthesis attribute IOBDELAY_TYPE of U1 is "VARIABLE";
//synthesis attribute IOBDELAY_VALUE of U1 is 0;
(
);
O(data_output)
I(data_input),
C(clkdiv),
CE(dlyce),
INC(dlyinc),
RST(dlyrst)
shows the IDELAYCTRL primitive.
Figure 7-15, page
Figure 7-13: IDELAYCTRL Primitive
www.xilinx.com
343), to reduce the effects of process, voltage, and
IDELAYCTRL_RPW
REFCLK
RST
IDELAYCTRL
ug070_7_13_080104
RDY
is required. IDELAYCTRL must be reset
ILOGIC Resources
341
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