IDTSTAC9753XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9753XXTAEB2XR Datasheet - Page 17

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IDTSTAC9753XXTAEB2XR

Manufacturer Part Number
IDTSTAC9753XXTAEB2XR
Description
IC CODEC AC'97 MIC/JACK 48-QFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Audio Codec '97r
Datasheet

Specifications of IDTSTAC9753XXTAEB2XR

Resolution (bits)
20 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Voltage - Supply, Analog
3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
STAC9753XXTAEB2XR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDTSTAC9753XXTAEB2XR
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
2.2.3.
2.2.4.
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BLT_CLK high pulse width (Note 1)
BIT_CLK low pulse width (Note 1)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Note:
XTL_OUT Pin Config CID1 Pin Config CID0 Pin Config
B I T _ C L K
short to ground
short to ground
short to ground
short to ground
XTAL or open
XTAL or open
XTAL or open
S Y N C
Clocks
STAC9752/9753 Crystal Elimination Circuit and Clock Frequencies
The STAC9752/9753 supports several clock frequency inputs as described in the following table. In
general, when a 24.576 MHz crystal is not used, the XTALOUT pin should be tied to ground. This
short to ground configures the part into an alternate clock mode and enables an on board PLL.
XTAL
1.
CODEC Modes:
P = The STAC9752/9753 as a Primary CODEC.
S = The STAC9752/9753 as a Secondary CODEC.
Worst case duty cycle restricted to 45/55.
Parameter
pulldown
pulldown
pulldown
pulldown
float
float
float
float
Tsync_high
T c l k _ h i g h
Figure 4. Clocks Timing
Table 1. Clock Mode Configuration
pulldown
pulldown
pulldown
pulldown
17
T c l k _ p e r i o d
float
float
float
float
T s y n c _ p e r i o d
14.31818 MHz source
Tsync_period
Clock Source Input
24.576 MHz source
Tclk_period
Tsync_high
12.288 MHz bit clk
12.288 MHz bit clk
12.288 MHz bit clk
Tsync_low
Tclk_high
24.576 MHz xtal
Tclk_low
Symbol
27 MHz source
48 MHz source
T c l k _ l o w
Tsync_low
STAC9752/9753
Min
36
36
-
-
-
-
-
-
-
CODEC Mode CODEC ID
12.288
81.4
40.7
40.7
48.0
20.8
19.5
Typ
750
1.3
P
S
S
S
P
P
P
P
Max
45
45
-
-
-
-
-
-
-
REV 3.3 1206
Units
MHz
KHz
0
1
2
3
0
0
0
0
ns
ps
ns
ns
s
s
s

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