IDTSTAC9753XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9753XXTAEB2XR Datasheet - Page 26

• Manufacturer Part Number: IDTSTAC9753XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
4.4.
4.5.
4.3.3.
4.5.1.
Clocking for Multiple CODEC Implementations
STAC9752/9753 as a Primary CODEC
CODEC ID Strapping
Audio CODECs in the 48-pin package use pins 45 and 46 (defined as ID0# and ID1#) as strapping
(i.e. configuration) pins to configure the CODEC ID. The ID0# and ID1# strapping bits adopt inverted
polarity and default to 00 = Primary (via a weak internal pullup) when left floating. This eliminates the
need for external resistors for CODECs configured as Primary, and maintains backward compatibil-
ity with existing layouts that treat pins 45 and 46 as “no connect” or cap to ground. Pulldowns are
typically 0-10 k
To keep the system synchronous, all Primary and Secondary CODEC clocking must be derived from
the same clock source, so all CODECs are operating on the same time base. In addition, all AC-Link
protocol timing must be based on the BIT_CLK signal, to ensure that everything on the AC-Link will
be synchronous.
The following are potential 24.576 MHz clock options available to a Secondary CODEC:
•
•
•
Primary devices are required to support correctly any of the following clocking options:
•
•
•
The Primary device may also, optionally, support the following clocking option:
•
STAC9752/9753 as a Secondary CODEC
Secondary devices are required to function correctly using one or more of the following clocking
options:
•
•
Using an external 24.576 MHz signal source (external oscillator or AC‘97 Digital Controller).
Using the Primary’s XTAL_OUT.
Using the Primary’s BIT_CLK output to derive 24.576 MHz.
See section 2.2.4: page17 for supported clock frequencies and configurations.
24.576 MHz crystal attached to XTAL_IN and XTAL_OUT.
24.576 MHz external oscillator provided to XTAL_IN.
12.288 MHz oscillator provided to the BIT_CLK input.
See section 2.2.4: page17 for supported clock frequencies and configurations.
24.576 MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary
24.576 MHz clock).
BIT_CLK input provided by the Primary. In this mode, a clock at XTAL_IN (Pin 2) is ignored.
See section 2.2.4: page17 for supported clock frequencies and configurations.
14.318 MHz external oscillator provided to XTAL_IN.
CID1 (pin 46)
pulldown
pulldown
NC
NC
Table 3. Recommended CODEC ID strapping
and connected to Digital (not Analog) Ground.
26
CID0 (pin 45)
pulldown
pulldown
NC
NC
STAC9752/9753
Secondary ID = 01
Secondary ID = 10
Secondary ID = 11
Primary ID = 00
Configuration
REV 3.3 1206