IDTSTAC9753XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9753XXTAEB2XR Datasheet - Page 33

• Manufacturer Part Number: IDTSTAC9753XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
SDATA_OUT
A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97
CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Con-
troller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posi-
tion is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97
CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time aligned.
SDATA_OUT’s composite stream is sent MSB first, with all non-valid slots bit positions stuffed with 0
by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and valid time slot, the
AC‘97 Controller always stuffs the trailing non-valid bit positions of the 20-bit slot with 0.
As an example, consider an 8-bit sample stream that is being played out to one of the STAC9752/
9753 DACs. The first 8 bit-positions are presented to the DAC (MSB first) followed by the next 12
bit-positions which are stuffed with 0 by the AC‘97 Controller. This ensures that regardless of the
resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least
significant bits.
When mono audio sample streams are output from the AC‘97 Controller, it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
BIT_CLK
End of previous audio frame
SYNC
S D A T A _ O U T
B I T _ C L K
E n d o f p r e v i o u s a u d i o f r a m e
12.288 MHz
Frame
valid
S Y N C
Figure 16. Start of an Audio Output Frame
Figure 15. AC-Link Audio Output Frame
slot1
Tag Phase
slot2
("1" = time slot contains valid PCM data)
a s s e r t e d
Time Slot "Valid" Bits
S Y N C
slot(12)
"0"
d e t e c t e d b y
33
CID1 CID0
S Y N C
c o d e c
F r a m e
v a l i d
19
Slot 1
s l o t 1
S D A T A _ O U T
b i t o f f r a m e
"0"
f i r s t
s l o t 2
19
STAC9752/9753
Slot 2
20.8 uS (48 kHZ)
Data Phase
"0"
19
Slot 3
"0"
19
REV 3.3 1206
Slot 12
"0"