IDTSTAC9753XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9753XXTAEB2XR Datasheet - Page 36

• Manufacturer Part Number: IDTSTAC9753XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
5.4.
5.3.8.
AC-Link Input Frame (SDATA_IN)
SDATA_IN
BIT_CLK
End of previous audio frame
Slot 12: Audio GPIO Control Channel
AC-Link output frame slot 12 contains the audio GPIO control outputs.
The AC-Link input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC‘97 Controller. As is the case for audio output frame, each AC-Link input frame con-
sists of 12 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are used
for AC-Link protocol infrastructure.
The following diagram illustrates the time slot-based AC-Link protocol.
A new AC-Link input frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97
CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97
CODEC transitions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit
position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the
AC‘97 Controller on the falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time aligned.
SDATA_IN’s composite stream is MSB first with all non-valid bit positions (for assigned and/or unas-
signed time slots) stuffed with 0 by the AC‘97 CODEC. SDATA_IN data is sampled on the falling
edges of BIT_CLK.
SYNC
S D A T A _ I N
12.288 MHz
B I T _ C L K
Frame
valid
E n d o f p r e v i o u s a u d i o f r a m e
Figure 17. STAC9752/9753 Audio Input Frame
S Y N C
slot1 slot2
Figure 18. Start of an Audio Input Frame
Tag Phase
("1" = time slot contains valid PCM data)
Time Slot "Valid" Bits
slot(12)
"0"
36
"0"
d e t e c t e d
S Y N C
"0"
C o d e c
R e a d y
19
Slot 1
s l o t 1
S D A T A _ O U T
b i t o f f r a m e
"0"
f i r s t
s l o t 2
19
Slot 2
STAC9752/9753
20.8 uS (48 kHZ)
Data Phase
"0"
19
Slot 3
"0"
19
REV 3.3 1206
Slot 12
"0"