IDTSTAC9753XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9753XXTAEB2XR Datasheet - Page 57

• Manufacturer Part Number: IDTSTAC9753XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.1.17.
Bit(s) Reset Value
14-13
Bit(s)
15
12
15:4
3:2
1:0
D15
D7
I4
This register is used to control the 3D stereo enhancement function, IDT Surround 3D (SS3D), built
into the AC'97 component. Note that register bits DP3-DP2 are used to control the separation ratios
in the 3D control for LINE_OUT. SS3D provides for a wider soundstage extending beyond the nor-
mal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to
1 to enable SS3D functionality to allow the bits in 22h to take effect. The three separation ratios are
implemented. The separation ratio defines a series of equations that determine the amount of depth
difference (High, Medium, and Low) perceived during 2-channel playback. The ratios provide for
options to narrow or widen the soundstage.
Audio Interrupt and Paging (24h)
Default: 0000h
Reset Value
0
0
0
0
0
0
D14
D6
I3
Read / Write
Read / Write
RESERVED
Read Only
Access
RESERVED
RESERVED
DP3, DP2
Name
D13
D5
I2
Name
I3-I2
I4
I1
Bits not used, should read back 0
LINE_OUT SEPARATION RATIO
DP3 DP2 effect
Bits not used, should read back 0
0
0
1
1
D12
57
D4
0 = Interrupt is clear
1 = Interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink
will follow this bit change when interrupt enable (I0) is unmasked.
Interrupt Cause
00 = Reserved
01 = Sense Cycle Complete, sense info available.
10 = Change in GPIO input status
11 = Sense Cycle Complete and Change in GPIO input status.
These bits will reflect the general cause of the first interrupt event
generated. It should be read after interrupt status has been
confirmed as interrupting. The information should be used to scan
possible interrupting events in proper pages.
Sense Cycle
0 = Sense Cycle not in Progress
1 = Sense Cycle Start.
Writing a 1 to this bit causes a sense cycle start if supported. If
sense cycle is not supported this bit is read only.
I1
0
1
0
1
4.5 ( MED )
0 ( OFF )
3 ( LOW )
6 ( HIGH )
PG3
D11
D3
I0
Description
STAC9752/9753
Description
PG2
D10
D2
RESERVED
PG1
D9
D1
REV 3.3 1206
PG0
D8
D0