IDTSTAC9753XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9753XXTAEB2XR Datasheet - Page 38

• Manufacturer Part Number: IDTSTAC9753XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
5.4.3.
5.4.4.
5.4.5.
5.4.6.
5.4.7.
The AC-Link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY
indicates valid Status Address Port data (Control Register Index). The CODEC should only set
SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previ-
ous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the
Slot 1 tag bit.
SLOTREQ bits are always 0 in the following cases:
•
•
SLOTREQ bits are only set to 1 by the CODEC in the following case:
•
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
If Slot 2 is tagged invalid by AC‘97, then the entire slot will be stuffed with 0 by AC‘97.
Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of STAC9752/9753 input MUX, post-ADC.
STAC9752/9753 ADCs are implemented to support 20-bit resolution.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9752/9753 input MUX, post-ADC.
STAC9752/9753 ADCs are implemented to support 20-bit resolution.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Slot 5: Modem Line 1 ADC
Audio input frame slot 5 is not used by the STAC9752/9753 and is always stuffed with 0.
Slot 6 - 9: ADC
The left and right ADC channels of the STAC9752/9753 may be assigned to slots 6&9 by Register
6Eh.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
19:4
fixed rate mode (VRA = 0)
inactive (powered down) ADC channel
Variable rate audio mode (VRA = 1) AND active (power ready) ADC AND a non-48 KHz ADC
sample rate AND CODEC does not need a sample
Bit
3:0
Control Register Read Data
Description
Reserved
Table 10. Status Data Port Bit Assignments
38
Stuffed with 0 if tagged “invalid”
Stuffed with 0
STAC9752/9753
Comments
REV 3.3 1206