ISP1181ABSUM ST-Ericsson Inc, ISP1181ABSUM Datasheet - Page 26

• Manufacturer Part Number: ISP1181ABSUM
• Description: IC USB HOST CTRL FULL-SPD 48HVQF
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1181ABSUM

• Controller Type: USB Peripheral Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 26mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1181ABS-T; ISP1181ABS-T

Philips Semiconductors
Table 13:
[1]
[2]
[3]
[4]
[5]
[6]
[7]
9397 750 13959
Product data
Name
Unstall Endpoint n
(n = 1 to 14)
Check Control OUT Status
Check Control IN Status
Check Endpoint n Status
(n = 1 to 14)
Acknowledge Setup
General commands
Read Control OUT Error Code
Read Control IN Error Code
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read Scratch Register
Read Frame Number
Read Chip ID
Read Interrupt Register
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
In 8-bit bus mode this command requires more time to complete than other commands. See
During isochronous transfer in 16-bit mode, because N
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1181A.
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1181A.
Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.
Command and register summary
[7]
12.1.1 Write/Read Endpoint Configuration
12.1 Initialization commands
[7]
[7]
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1181A and to
perform a device reset.
This command is used to access the Endpoint Configuration Register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in
The allocation of FIFO memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and be configured with their default values (see
allocation starts when endpoint 14 has been configured.
Destination
Endpoint 1 to 14
Endpoint Status Image Register
endpoint 0 OUT
Endpoint Status Image Register
endpoint 0 IN
Endpoint Status Image Register n
endpoint 1 to 14
Endpoint 0 IN and OUT
Error Code Register
endpoint 0 OUT
Error Code Register
endpoint 0 IN
Error Code Register
endpoint 1 to 14
all registers with write access
Scratch Register
Frame Number Register
Chip ID Register
Interrupt Register
…continued
Rev. 05 — 08 December 2004
1023, the firmware must take care of the upper byte.
Table
14. A bus reset will disable all endpoints.
Code (Hex)
82 to 8F
D0
D1
D2 to DF
F4
A0
A1
A2 to AF
B0
B2/B3
B4
B5
C0
Full-speed USB peripheral controller
Table
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
58.
Transaction
-
read 1 byte
read 1 byte
read 1 byte
-
read 1 byte
read 1 byte
read 1 byte
write 2 bytes
write/read 2 bytes
read 1 or 2 bytes
read 2 bytes
read 4 bytes
Table
[3]
ISP1181A
4). Automatic FIFO
[2]
[2]
[2]
[2]
[2]
[2]
[1]
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