IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 12

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
DESCRIPTION
Controlled by software, the IDT82V2108 can be globally configured as
an Octal E1 or T1/J1 Framer. When E1 or T1/J1 has been set globally,
the operation mode of each of the eight framers can be configured inde-
pendently. The configuration is performed through a parallel Multiplexed/
Non-Multiplexed microprocessor interface.
signaling extraction and insertion, alarm and test signals generation and
detection in a single chip. It also integrates up to three HDLC receivers
and HDLC transmitters for each of the eight framers.
be Basic Frame, CRC Multi-Frame and Signaling Multi-Frame. The
framing can also be bypassed (unframed mode). It detects and indicates
the event of out of Basic Frame Synchronization, out of CRC Multi-
Frame and out of Signaling Multi-Frame. It also detects and indicates
the Remote Alarm Indication signal and the Remote Signaling Multi-
Frame Alarm Indication signal. The Red and AIS alarms are monitored.
Basic Frame Alignment Signal errors, Far End Block Errors (FEBE) and
CRC errors are counted. Up to three HDLC links are provided to extract
the HDLC message on TS16, the Sa National bits and/or any arbitrary
time slot. An Elastic Store Buffer that optionally supports slip buffering
and adaptation to backplane timing is provided. In E1 receive path, sig-
naling debounce, signaling freezing, idle code substitution, digital milli-
watt code insertion, trunk conditioning, data inversion and pattern
generation or detection are also supported on a per-timeslot basis.
generate Basic Frame, CRC Multi-Frame and Signaling Multi-Frame.
The framing can also be disabled (unframed mode). It can also transmit
Remote Alarm Indication signal, Remote Signaling Multi-Frame Alarm
Indication signal, AIS signal and FEBE. Up to three HDLC links are pro-
vided to insert the HDLC message on TS16, the Sa National bits and/or
any arbitrary time slot. The signaling insertion, idle code substitution,
data insertion, data inversion and test pattern generation or detection
are also supported on a per-timeslot basis.
multiplexed to or from one of the two 8.192M bit/s buses.
to be in Super Frame (SF) or Extended Super Frame (ESF) formats.
The framing can also be bypassed (unframed mode). It detects and indi-
cates the out of SF/ESF synchronization event, the Yellow, Red and AIS
alarms. It also detects the presence of inband loopback codes, bit ori-
ented message. Frame Alignment Signal errors, CRC-6 errors, out of
SF/ESF events and Frame Alignment position changes are counted. Up
to two HDLC links are provides to extract the HDLC message on the F-
bit or any arbitrary channels in ESF format. An Elastic Store Buffer that
optionally supports controlled slip and adaptation to backplane timing is
provided. In T1/J1 receive path, signaling debounce, signaling freezing,
idle code substitution, digital milliwatt code insertion, idle code insertion,
data inversion and pattern generation or detection are also supported on
a per-channel basis.
to generate SF or ESF. The framing can also be disabled (unframed
Description
The IDT82V2108 is a flexible feature-rich octal T1/E1/J1 Framer.
The IDT82V2108 realizes frame synchronization, frame generation,
In E1 Mode, the receive path of each framer can be configured to
In E1 mode, the transmit path of each framer can be configured to
In E1 mode, any four of the eight framers can be multiplexed or de-
In T1/J1 mode, the receive path of each framer can be configured
In T1/J1 mode, the transmit path of each framer can be configured
2
mode). It can also transmit Yellow signal and AIS signal. Inband loop-
back codes and bit oriented message can also be transmitted. Up to two
HDLC links are provided to insert the HDLC message on the F-bit or any
arbitrary channels in ESF format. The signaling insertion, idle code sub-
stitution, data insertion, data inversion and test pattern generation or
detection are also supported on a per-channel basis.
to/from the data stream of 2.048M bit/s on the system side by software
configuration. In addition, any four of the eight framers can be multi-
plexed or de-multiplexed to or from one of the two 8.192M bit/s buses.
In T1/J1 mode, the data stream of 1.544M bit/s can be converted
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009