IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 99

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
3.21
3.21.1
sampled on the active edge of LRCKn. The active edge of LRCKn is
chosen by the RCKFALL (b7, E1-001H).
LTDn pin is updated on the active edge of LTCKn. The active edge of
LTCKn is chosen by the LTCKRISE (b0, E1-002H). All ones will be
forced to transmit on the LTDn pin when the TAISEN (b6, E1-002H) is
configured. All zeros will also be forced to transmitted when the TXDIS
(b0, E1-007H) is configured.
3.21.2
sampled on the active edge of LRCKn. The active edge of LRCKn is
chosen by the LRCKFALL (b2, T1/J1-003H).
LTDn pin is updated on the active edge of LTCKn. The active edge of
LTCKn is chosen by the LTCKRISE (b0, T1/J1-004H). All ones will be
forced to transmitted on the LTDn pin when the TAISEN (b6, T1/J1-
004H) is configured. All zeros will also be forced to transmit when the
TXDIS (b0, T1/J1-00AH) is configured.
Functional Description
On the receive line interface, the received data on the LRDn pin is
On the transmit line interface, the data to be transmitted on the
On the receive line interface, the received data on the LRDn pin is
On the transmit line interface, the data to be transmitted on the
LINE INTERFACE
E1 MODE
T1/J1 MODE
89
3.22
3.22.1
has occurred in the device, reading the INT[8:1] (b7~0, E1-00BH) will
find in which framer the interrupt occurs. After reading the INT register,
the interrupt source bits from the interrupting framer are read. The Inter-
rupt Source bits (PMON [b7, E1-005H], FRMG [b6, E1-005H], FRMP
[b5, E1-005H], PRGD [b4, E1-005H], ELSB [b3, E1-005H], RHDLC#1
[b2, E1-005H], RHDLC#2 [b1, E1-005H], RHDLC#3 [b0, E1-005H],
TRSI [b7, E1-006H], TJAT [b5, E1-006H], RJAT [b4, E1-006H],
THDLC#1 [b3, E1-006H], THDLC#2 [b2, E1-006H], THDLC#3 [b1, E1-
006H] and RCRB [b0, E1-006H]) will be logic 1 if there are interrupts in
the corresponding block. To find the eventual interrupt sources, the inter-
rupt Indication and Status bits in the block are polled if their Interrupt
Enable bits are enabled. Then the sources are served after they are
found.
3.22.2
has occurred in the device, reading the INT[8:1] (b7~0, T1/J1-00EH) will
find that in which framer the interrupt occurs. After reading the INT regis-
ter, the interrupt source bits from the interrupting framer are read. The
Interrupt Source bits (PMON [b7, T1/J1-008H], IBCD [b6, T1/J1-008H],
FRMP [b5, T1/J1-008H], PRGD [b4, T1/J1-008H], ELSB [b3, T1/J1-
008H], RHDLC#1 [b2, T1/J1-008H], RBOM [b1, T1/J1-008H], ALMD
[b0, T1/J1-008H], RHDLC#2 [b7, T1/J1-009H], TJAT [b5, T1/J1-009H],
RJAT [b4, T1/J1-009H], THDLC#1 [b3, T1/J1-009H], THDLC#2 [b2, T1/
J1-009H] and RCRB [b0, T1/J1-009H]) will be logic 1 if there are inter-
rupts in the corresponding block. To find the eventual interrupt sources,
the interrupt Indication and Status bits in the block are polled if their
Interrupt Enable bits are enabled. Then the sources are served after
they are found.
provided to route to the pending parity error.
When the INT pin asserts low, which means at least one interrupt
When the INT pin asserts low, which means at least one interrupt
However, another Interrupt Source bit PRTY (b6, T1/J1-009H) is
INTERRUPT SUMMARY
E1 MODE
T1/J1 MODE
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009