IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 33

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
RHDLCSEL[1:0] (b7~6, T1/J1-00DH), one of the two HDLC Receiver
blocks is accessible to the microprocessor. The HDLC#1 extracts the
HDLC link in the DL of the F-bit (its position is shown in Table 4). The
HDLC#2 extracts the HDLC link from one of the channels which position
is defined as follows:
T1/J1-070H) to choose the even and/or odd frames;
the assigned frame;
assigned channel.
enabled only if the EN (b0, T1/J1-054H) is set to logic 1.
the E1 mode (refer to Figure 5).
data whose stuffed zeros have been removed and the FCS. However,
when the address matching is enabled, the first and/or second byte
compares with the address setting in the PA[7:0] (b7~0, T1/J1-058H)
and the SA[7:0] (b7~0, T1/J1-059H) and only the data matching the
address mode set in the MEN (b3, T1/J1-054H) and the MM (b2, T1/J1-
054H) is stored into the FIFO. When the address matching is disabled,
the entire HDLC packet is stored. The first 7E opening flag which acti-
vates the HDLC link and the 7F abort sequence which deactivates the
HDLC link will also be converted into dummy bytes and stored in the
FIFO. These two types of flags will also assert the COLS (b5, T1/J1-
056H) to indicate the HDLC link status change. The content in the FIFO
is read in the RD[7:0] (b7~0, T1/J1-057H), and the status of the bytes
will be reflected in the PBS[2:0] (b3~1, T1/J1-056H). Both of the two reg-
isters can not be accessed at a rate greater than 1/15 of the XCK rate.
FE (b7, T1/J1-056H) will be set. If data is still written into the FIFO when
the FIFO is already full, the FIFO will be over-written. The over-written
condition will be indicated by the OVR (b6, T1/J1-056H) and force the
FIFO to be cleared.
packet was received whether there were FCS errors or non-integer num-
ber of bytes errors in it or not.
stream;
logic 1.
and the latter two methods will also clear the FIFO and interrupts. A new
search for the 7E opening flag is also initiated.
the all ones data and activates the HDLC link;
Functional Description
1. Set the DL2_EVEN (b7, T1/J1-070H) and/or the DL2_ODD (b6,
2. Set the DL2_TS[4:0] (b4~0, T1/J1-070H) to define the channel of
3. Set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to select the bits of the
All the functions of the selected HDLC Receiver block will be
The structure of the HDLC packet is the same as it is described in
A FIFO buffer is used to store the HDLC packet, that is, to store the
The depth of the FIFO is 128 bytes. When the FIFO is empty, the
A logic 1 in the PKIN (b4, T1/J1-056H) indicates a non-abort HDLC
The HDLC packet can be forced to terminate by four means:
1. The 7F abort sequence is received;
2. More than 15 successive logic ones are received in the data
3. Set the TR (b2, T1/J1-054H) to logic 1;
4. Set the EN (b1, T1/J1-054H) from logic 1 to logic 0 and back to
All the above methods will deactivate the HDLC link immediately
The interrupt sources in this block are:
1. Receiving the first 7E opening flag sequence which terminates
2. Receiving the 7E closing flag sequence;
3. Receiving the abort sequence;
23
INTC[6:0] (b6~0, T1/J1-055H);
056H) high. Then the INT pin will be driven low to report the interrupt if
the INTE (b7, T1/J1-055H) is logic 1.
4. Exceeding the set point of the FIFO which is defined in the
5. Over-writing the FIFO.
Any one of the interrupt sources will assert the INTR (b0, T1/J1-
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009