IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 212

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
E1 PRGD Control (070H)
PDR[1:0]:
PS:
TINV:
RINV:
AUTOSYNC:
MANSYNC:
ommended to ensure that the detector works correctly.
Programming Information
Bit Name
Default
Bit No.
Type
The PDR[1:0] define the function of the four PRGD Pattern Detector registers:
= 0: A pseudo-random pattern is generated/detected by the PRGD.
= 1: A repetitive pattern is generated/detected by the PRGD.
This bit should be set first of all the PRGD registers.
= 0: Disable the inversion of the generated pattern before being transmitted.
= 1: Enable the inversion of the generated pattern before being transmitted.
= 0: Disable the inversion of the received pattern before being processed.
= 1: Enable the inversion of the received pattern before being processed.
= 0: Disable automatically re-searching for the synchronization of the pattern when the PRGD pattern is out of synchronization.
= 1: Enable automatically re-searching for the synchronization of the pattern when the PRGD pattern is out of synchronization.
Trigger on the rising edge. A transition from logic 0 to logic 1 on this bit manually initiates a re-search for the synchronization of a pattern.
Every time when the setting of the PRGD registers is changed or the detector data source changes, a manual synchronization operation is rec-
PDR[1]
R/W
7
0
(The #1 is the LSB, while the #4 is the MSB.)
PDR[0]
R/W
6
0
PDR[1:0]
0 0, 0 1
1 0
1 1
Reserved
5
PRGD Pattern Detector Registers (#1 ~ #4)
R/W
PS
4
0
202
Pattern Receive
Error Count
Bit Count
TINV
R/W
3
0
RINV
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
AUTOSYNC
R/W
1
1
March 5, 2009
MANSYNC
R/W
0
0