IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 160
IDT82V2108BB
Manufacturer Part Number
IDT82V2108BB
Description
IC FRAMER T1/J1/E1 8CH 144-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108BB
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-BGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108BB
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IDT82V2108
E1 RJAT Interrupt Status (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H)
OVRI:
UNDI:
E1 RJAT Reference Clock Divisor (N1) Control (021H, 0A1H, 121H, 1A1H, 221H, 2A1H, 321H, 3A1H)
input reference clock and the frequency applied to the phase discriminator input.
E1 RJAT Output Clock Divisor (N2) Control (022H, 0A2H, 122H, 1A2H, 222H, 2A2H, 322H, 3A2H)
output smoothed clock and the frequency applied to the phase discriminator input.
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
If data is still attempted to write into the FIFO when the FIFO is already full, the overwritten event will occur.
= 0: The RJAT FIFO is not overwritten.
= 1: The RJAT FIFO is overwritten.
This bit is cleared to ‘0’ when it is read.
If data is still attempted to read from the FIFO when the FIFO is already empty, the under-run event will occur.
= 0: The RJAT FIFO is not under-run.
= 1: The RJAT FIFO is under-run.
This bit is cleared to ‘0’ when it is read.
These bits define a binary number. The (N1[7:0] + 1) is the divisor of the input reference clock, which is the ratio between the frequency of the
Writing to this register will reset the DPLL in the RJAT.
These bits define a binary number. The (N2[7:0] + 1) is the divisor of the output smoothed clock, which is the ratio between the frequency of the
Writing to this register will reset the DPLL in the RJAT.
N1[7]
N2[7]
R/W
R/W
7
7
0
7
0
N1[6]
N2[6]
R/W
R/W
6
0
6
0
6
N1[5]
N2[5]
R/W
R/W
5
5
1
5
1
Reserved
N1[4]
N2[4]
R/W
R/W
4
4
0
4
0
150
N1[3]
N2[3]
R/W
R/W
3
3
1
3
1
N1[2]
N2[2]
R/W
R/W
2
1
2
1
2
T1 / E1 / J1 OCTAL FRAMER
OVRI
N1[1]
N2[1]
R/W
R/W
R
X
1
1
1
1
1
March 5, 2009
UNDI
N1[0]
N2[0]
R/W
R/W
R
X
0
0
1
0
1
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