IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 276
IDT82V2108BB
Manufacturer Part Number
IDT82V2108BB
Description
IC FRAMER T1/J1/E1 8CH 144-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108BB
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-BGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108BB
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IDT82V2108
T1 / J1 RESI Time Slot Offset (077H, 0F7H, 177H, 1F7H, 277H, 2F7H, 377H, 3F7H)
001H] are set to ‘10’), these bits determine the channel offset between RSCFS and the start of the corresponding frame on RSDn (and RSSIGn).
MRSSIG.
disabled. Thus, the TSOFF must be set to ‘0’.
Programming Information
Bit Name
Default
Bit No.
Type
In Receive Clock Slave mode, when the data rate on the system side is 2.048 Mbit/s (the RSCCK2M [b4, T1/J1-001H] and RSCCK8M [b3, T1/J1-
In Receive Multiplexed mode, these bits determine the channel offset between MRSCFS and the start of the corresponding frame on MRSD and
In Receive Clock Slave mode, when the data rate on the system side is 1.544 Mbit/s, and in Receive Clock Master mode, the channel offset is
They define a binary number. The offset can be set from 0 to 127 channels.
Reserved
7
TSOFF[6]
R/W
0
6
TSOFF[5]
R/W
5
0
TSOFF[4]
R/W
4
0
266
TSOFF[3]
R/W
3
0
TSOFF[2]
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
TSOFF[1]
R/W
1
0
March 5, 2009
TSOFF[0]
R/W
0
0
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