IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 226

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
T1 / J1 Interrupt Source #2 (009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H)
ister must be read.
T1 / J1 Diagnostics (00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH)
LINELB:
and clock (LRDn and LRCKn). The loop back data stream can pass through the Receive Jitter Attenuator or bypass the Receive Jitter Attenuator (if
the Receive Jitter Attenuator is configured to be bypassed)
DDLB:
clock (LTDn and LTCKn) without the Receive Jitter Attenuator.
TXMFP:
channel.
TXDIS:
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Type
Type
Bits in this register indicate which function block introduced an interrupt signal on the INT pin.
The PRTY bit indicates a pending parity error indication needs serving in the Backplane Parity Configuration and Status registers.
Reading this register does not clear the interrupt indication. To clear the interrupt indication on the INT pin, the corresponding interrupt status reg-
Line Loop back means that the transmit line interface data and clock (LTDn and LTCKn) are internal directly comes from the received line data
= 0: Line loop back is disabled.
= 1: Line loop back is enabled.
Digital Loop back means that the received line data and clock (LRDn and LRCKn) are internal directly comes from the transmit line data and
= 0: Digital loop back is disabled.
= 1: Digital loop back is enabled.
This bit controls whether mimic pattern is generated. The mimic pattern is a copy of the F-bit. The mimic pattern is generated in the 1st bit of each
= 0: Mimic pattern is not generated.
= 1: Mimic pattern is generated.
= 0: Normal transmission.
= 1: Force the data to be transmitted on the TLDn pin to be all ‘Zero’s.
RHDLC#2
R/W
7
0
7
Reserved
PRTY
R/W
6
0
6
TJAT
R/W
5
0
5
LINELB
RJAT
R/W
R/W
4
0
4
0
216
THDLC#1
Reserved
R/W
3
0
3
THDLC#2
DDLB
R/W
R/W
2
0
2
0
T1 / E1 / J1 OCTAL FRAMER
Reserved
TXMFP
R/W
1
1
0
March 5, 2009
TXDIS
RCRB
R/W
R/W
0
0
0
0