IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 128

• Manufacturer Part Number: IDT82V2108BB
• Description: IC FRAMER T1/J1/E1 8CH 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108BB

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108BB

IDT82V2108
- Polling Mode
OVRE (b2, T1/J1-037H), UDRE (b1, T1/J1-037H) and LFILLE (b0, T1/
J1-037H) should be set to logic 0. The THDLC Lower Transmit Thresh-
example is shown in Table 55.
Operation
In packet transmission polling mode, the FULLE (b3, T1/J1-037H),
To summarize the procedure of using HDLC Transmit, a complete
Figure 82. Polling Mode in T1/J1 Mode HDLC Transmitter
Y
into the THDLC FIFO
be tarnsmitted
interrupt status
More data to
Write the data
Read THDLC
THDLC initial
available
FULL=1
Data is
Set EOM
Y
N
N
118
old should be set to such a value that sufficient warning of an underrun
is given. The procedure shown in Figure 82 should be followed.
Table 55: Example for Using HDLC Transmitter
N
Register
Y
034H
00DH
070H
071H
037H
039H
039H
039H
039H
039H
039H
039H
039H
034H
034H
Wait, Until FULL=0
or BBLFILL=1
Value
BCH
DEH
C4H
FFH
C3H
0FH
9AH
FFH
8BH
58H
83H
12H
34H
56H
78H
THDLC #2 is selected. The HDLC Transmit is
All 8 bits are selected.
accessible to the CPU interface.
TS4 of even frames and odd frames is selected
The function of the THDLC #2 is enabled. The FCS
is enabled and the THDLC FIFO is reset.
Enable the THDLC Interrupt Enable bits.
Write data into THDLC FIFO.
End of packet and set the EOM to ‘1’.
T1 / E1 / J1 OCTAL FRAMER
Description
March 5, 2009