IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 270
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IDT82V2108BB
Manufacturer Part Number
IDT82V2108BB
Description
IC FRAMER T1/J1/E1 8CH 144-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108BB
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-BGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108BB
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IDT82V2108
that the detector works correctly.
T1 / J1 PRGD Interrupt Enable / Status (061H)
SYNCE:
BEE:
XFERE:
SYNCV:
SYNCI:
BEI:
XFERI:
OVR:
Programming Information
Bit Name
Default
Bit No.
Type
Each time the value of the PRGD registers is changed or the detector data source changes, a manual sync operation is recommended to ensure
= 0: Disable the interrupt on the INT pin when the SYNCI is logic one.
= 1: Enable the interrupt on the INT pin when the SYNCI is logic one.
= 0: Disable the interrupt on the INT pin when at least one bit error has been detected in the received pattern.
= 1: Enable the interrupt on the INT pin when at least one bit error has been detected in the received pattern.
= 0: Disable the interrupt on the INT pin when the data in the PRGD pattern detector register is updated.
= 1: Enable the interrupt on the INT pin when the data in the PRGD pattern detector register is updated.
= 0: The pattern is out of synchronization (the pattern detector has detected 10 or more bit errors in a fixed 48-bit window).
= 1: The pattern is in synchronization (the pattern detector has observed at least 48 consecutive error-free bit periods).
= 0: There is no transition on the SYNCV.
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the SYNCV.
This bit is cleared to ‘0’ after the bit is read.
= 0: No bit error is detected in the received pattern.
= 1: At least one bit error has been detected in the received pattern.
This bit is cleared to ‘0’ after the bit is read.
= 0: The data in the PRGD pattern detector register is not updated.
= 1: The data in the PRGD pattern detector register is updated.
This bit is cleared to ‘0’ after the bit is read.
= 0: The PRGD pattern detector register is not overwritten.
= 1: The PRGD pattern detector register is overwritten.
This bit is cleared to ‘0’ after the bit is read.
SYNCE
R/W
7
0
BEE
R/W
6
0
XFERE
R/W
5
0
SYNCV
R
X
4
260
SYNCI
R
X
3
BEI
R
2
X
T1 / E1 / J1 OCTAL FRAMER
XFERI
R
X
1
March 5, 2009
OVR
R
X
0
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