PIC16F1947-I/PT Microchip Technology Inc., PIC16F1947-I/PT Datasheet - Page 253

• Manufacturer Part Number: PIC16F1947-I/PT
• Description: 64 TQFP 10x10x1mm TRAY28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1947-I/PT

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 54
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 28K Bytes
• Ram Size: 1K Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

24.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
TABLE 24-1:
 2010 Microchip Technology Inc.
ANSELA
APFCON
INTCON
PIE1
PIE4
PIR1
PIR4
SSPxBUF
SSPxCON1
SSPxCON3
SSPxSTAT
TRISA
TRISB
Legend:
Name
*
SPI OPERATION IN SLEEP MODE
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
Page provides register information.
Synchronous Serial Port Receive Buffer/Transmit Register
TMR1GIE
TMR1GIF
P3CSEL
ACKTIM
TRISA7
TRISB7
ANSA7
WCOL
Bit 7
SMP
GIE
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
SSPxOV
P3BSEL
TRISA6
TRISB6
ANSA6
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
—
—
P2DSEL
SSPxEN
TMR0IE
TRISA5
TRISB5
ANSA5
RC2IE
RC2IF
RCIE
RCIF
SCIE
Bit 5
D/A
P2CSEL
TRISA4
TRISB4
ANSA4
BOEN
TX2IE
TX2IF
Preliminary
INTE
TXIE
Bit 4
TXIF
CKP
P
P2BSEL
TRISA3
TRISB3
ANSA3
SDAHT
SSPIE
SSPIF
IOCIE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
—
—
S
PIC16F/LF1946/47
CCP2SEL
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISB2
ANSA2
Bit 2
R/W
—
—
SSPxM<3:0>
P1CSEL
TMR2IE
TMR2IF
TRISA1
TRISB1
BCL2IE
BCL2IF
ANSA1
AHEN
Bit 1
INTF
UA
P1BSEL
TMR1IE
TMR1IF
SSP2IE
SSP2IF
TRISA0
TRISB0
ANSA0
DHEN
IOCIF
Bit 0
DS41414B-page 253
BF
Register
on Page
247*
129
126
101
292
294
291
128
131
93
94
97
98