IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 110

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.27.1.1 Pattern Generator
per O.152 and 2
PATS[1:0] bits.
to ‘1’ on the TESTEN bit.
INV bit is set to ‘1’. Before the insertion, the generated pattern can be
inverted when the TINV bit is set.
3.27.1.2 Pattern Detector
pattern detector starts to extract the data. The extracted data is used to
re-generate a desired pattern which is selected by the PATS[1:0] bits.
Table 77: Related Bit / Register In Chapter 3.27.1
Functional Description
IDT82P2288
Note:
* ID means Indirect Register in the Receive & Transmit Payload Control function blocks.
Three patterns are generated: 2
The selected pattern is generated once there is a transition from ‘0’
A single bit error will be inserted to the generated pattern when the
When there is a transition from ‘0’ to ‘1’ on the TESTEN bit, the
PRBSMODE[1:0]
PRBSDIR
PATS[1:0]
TESTEN
SYNCV
SYNCE
SYNCI
BERE
TEST
RINV
TINV
BERI
INV
Bit
20
-1 pattern per O.150-4.5. They are selected by the
11
-1 pattern per O.150, 2
TPLC / RPLC / PRGD Test Configuration
ID * - Signaling Trunk Conditioning Code
PRGD Status/Error Control
PRGD Interrupt Indication
PRGD Control
Register
15
-1 pattern
110
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
The extracted data is compared with the re-generated pattern. If the
extracted data coincides with the pattern, the pattern is synchronized
and it will be indicated by the SYNCV bit. In synchronization state, each
mismatched bit will generate a PRGD Bit Error event. This event is
captured by the BERI bit and is forwarded to the Performance Monitor.
An interrupt reported on the INT pin will be enabled by the BERE bit if
the BERI bit is ‘1’. When there are more than 10-bit errors detected in
the fixed 48-bit window, the extracted data is out of synchronization and
it also will be indicated by the SYNCV bit. Any transition (from ‘1’ to ‘0’ or
from ‘0’ to ‘1’) on the SYNCV bit will set the SYNCI bit. An interrupt
reported on the INT pin will be enabled by the SYNCE bit if the SYNCI
bit is ‘1’.
inverted by setting the RINV bit.
Before the data extracted to the pattern detector, the data can be
RPLC & TPLC ID * - 41~58 (for T1/J1) / 41~4F & 51~5F (for E1)
0C7, 1C7, 2C7, 3C7, 4C7, 5C7, 6C7, 7C7
071, 171, 271, 371, 471, 571, 671, 771
072, 172, 272, 372, 472, 572, 672, 772
073, 173, 273, 373, 473, 573, 673, 773
Address (Hex)
March 04, 2009