IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 19

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

Pin Description
IDT82P2288
DS / RD / SCLK
RW / WR / SDI
VDDDIO
SPIEN
Name
TRST
TMS
TCK
TDO
TDI
High-Z
Power
Type
Input
Input
Input
Input
Input
Input
Input
K12, L12,
J12, K5,
Pin No.
F5, G5,
H5, J5,
N10
R13
R14
M12
P11
N11
T14
T15
T13
VDDDIO: 3.3 V I/O Power Supply
RW: Read / Write Select
In parallel Motorola mode, this pin is active high for read operation and active low for write operation.
WR: Write Strobe (Active Low)
In parallel Intel mode, this pin is active low for write operation.
SDI: Serial Data Input
In SPI mode, the address/control and/or data are serially input on this pin.
RW / WR / SDI is a Schmitt-trigger input.
DS: Data Strobe (Active Low)
In parallel Motorola mode, this pin is active low.
RD: Read Strobe (Active Low)
In parallel Intel mode, this pin is active low for read operation.
SCLK: Serial Clock
In SPI mode, this pin inputs the timing for the SDO and SDI pins. The signal on the SDO pin is updated on the falling
edge of SCLK, while the signal on the SDI pin is sampled on the rising edge of SCLK.
DS / RD / SCLK is a Schmitt-trigger input.
SPIEN: Serial Microprocessor Interface Enable
When this pin is low, the microprocessor interface is in parallel mode.
When this pin is high, the microprocessor interface is in SPI mode.
SPIEN is a Schmitt-trigger input.
TRST: Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. This pin is a Schmitt-triggered input with an internal pull-up resis-
tor. It must be connected to the RESET pin or ground when JTAG is not used.
TMS: Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. This pin is a
Schmitt-triggered input with an internal pull-up resistor.
TCK: Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is
clocked out of the device on the falling edge of TCK. This pin is a Schmitt-triggered input with an internal pull-up
resistor.
TDI: Test Input
The test data is sampled at this pin on the rising edge of TCK. This pin is a Schmitt-triggered input with an internal
pull-up resistor.
TDO: Test Output
The test data are output on this pin. It is updated on the falling edge of TCK. This pin is High-Z except during the
process of data scanning.
JTAG (per IEEE 1149.1)
Power & Ground
19
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Description
March 04, 2009