IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 284

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

E1 Overhead Interrupt Indication (061H, 161H, 261H, 361H, 461H, 561H, 661H, 761H)
TCRCEI:
TFEBEI:
ated.
FEBEI:
generated. During out of CRC Multi-Frame synchronization state, the Far End Block Error (FEBE) detection is suspended.
RAICRCI:
CFEBEI:
V52LINKI:
Programming Information
IDT82P2288
Bit Name
If the 4-bit Sa6 codeword of a CRC Sub Multi-Frame is matched with ‘0010’ or ‘0011’, the Network Terminal CRC Error event is generated.
= 0: No NT CRC Error event is detected.
= 1: The NT CRC Error event is detected.
This bit will be cleared if a ’1’ is written to it.
If the 4-bit Sa6 codeword of a CRC Sub Multi-Frame is matched with ‘0001’ or ‘0011’, the Network Terminal Far End Block Error event is gener-
= 0: No NT FEBE Error event is detected.
= 1: The NT FEBE Error event is detected.
This bit will be cleared if a ’1’ is written to it.
When CRC Multi-Frame is synchronized and any of the CRC error indication (E1 or E2) bits is received as a logic 0, a far end block error event is
= 0: No Far End Block Error (FEBE) event is detected.
= 1: The Far End Block Error (FEBE) event is detected.
This bit will be cleared if a ’1’ is written to it.
= 0: There is no status change on the RAICRCV bit (b, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RAICRCV bit (b2, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
= 0: There is no status change on the CFEBEV bit (b, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the CFEBEV bit (b, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
= 0: There is no status change on the V52LINKV bit (b, E1-04FH,...).
= 1: There is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the V52LINKV bit (b, E1-04FH,...).
This bit will be cleared if a ’1’ is written to it.
Default
Bit No.
Type
7
Reserved
6
TCRCEI
R
5
0
TFEBEI
R
4
0
284
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
FEBEI
R
3
0
RAICRCI
R
2
0
CFEBEI
R
1
0
March 04, 2009
V52LINKI
R
0
0