IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 170

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

T1/J1 RBIF TS Offset (049H, 149H, 249H, 349H, 449H, 549H, 649H, 749H)
TSOFF[6:0]:
start of the corresponding frame output on the RSDn/MRSDA(MRSDB) pin. The signaling bits on the RSIGn/MRSIGA(MRSIGB) pin are always per-
channel aligned with the data on the RSDn/MRSDA(MRSDB) pin.
offset can be configured from 0 to 127 channels (0 & 127 are included).
T1/J1 RBIF Bit Offset (04AH, 14AH, 24AH, 34AH, 44AH, 54AH, 64AH, 74AH)
EDGE:
BOFF[2:0]:
corresponding frame output on the RSDn/MRSDA(MRSDB) pin. The signaling bits on the RSIGn/MRSIGA(MRSIGB) pin are always per-channel
aligned with the data on the RSDn/MRSDA(MRSDB) pin.
Programming Information
IDT82P2288
Bit Name
Bit Name
These bits give a binary number to define the channel offset. The channel offset is between the framing pulse on the RSFSn/MRSFS pin and the
In Non-multiplexed mode, the channel offset can be configured from 0 to 23 channels (0 & 23 are included). In Multiplexed mode, the channel
This bit is valid when the CMS bit (b1, T1/J1-046H,...) is ‘1’.
= 0: The first active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSDA(MRSDB) and RSIGn/MRSIGA(MRSIGB) pins.
= 1: The second active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSDA(MRSDB) and RSIGn/MRSIGA(MRSIGB)
pins.
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the RSFSn/MRSFS pin and the start of the
Default
Default
Bit No.
Bit No.
Type
Type
Reserved
7
7
TSOFF6
R/W
6
0
6
Reserved
TSOFF5
R/W
5
0
5
TSOFF4
R/W
4
0
4
170
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
TSOFF3
EDGE
R/W
R/W
3
0
3
0
TSOFF2
BOFF2
R/W
R/W
2
0
2
0
TSOFF1
BOFF1
R/W
R/W
1
0
1
0
March 04, 2009
TSOFF0
BOFF0
R/W
R/W
0
0
0
0