IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 58

no-image

IDT82P2288BB

Manufacturer Part Number
IDT82P2288BB
Description
TXRX T1/J1/E1 8CHAN 256-PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Type
Transceiverr
Datasheet

Specifications of IDT82P2288BB

Protocol
IEEE 1149.1
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
82P2288BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT82P2288BB
Manufacturer:
IDT
Quantity:
6
Part Number:
IDT82P2288BB
Manufacturer:
IDT
Quantity:
917
Part Number:
IDT82P2288BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82P2288BB8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82P2288BBG
Manufacturer:
IDT
Quantity:
28
Part Number:
IDT82P2288BBG
Manufacturer:
WYC
Quantity:
3 000
Part Number:
IDT82P2288BBG
Manufacturer:
IDT Integrated Device Technolo
Quantity:
135
Part Number:
IDT82P2288BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82P2288BBG
Manufacturer:
XILINX
0
Part Number:
IDT82P2288BBG
Manufacturer:
IDT
Quantity:
20 000
Part Number:
IDT82P2288BBG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
3.10 ALARM DETECTOR
3.10.1 T1/J1 MODE
block (refer to Table 26).
Table 26: RED Alarm, Yellow Alarm & Blue Alarm Criteria
Functional Description
IDT82P2288
Note: * The Yellow Alarm can only be detected when the frame is synchronized.
Yellow
Alarm*
The RED alarm, Yellow alarm and Blue alarm are detected in this
(per T1.403,
(per T1.231)
Blue Alarm
RED Alarm
T1.231)
Format
T1 ESF
Format
Format
Format
J1 ESF
Format
T1 SF/
T1 DM
J1 SF
SLC-
96
The out of SF/ESF/T1 DM/SLC-96 syn-
chronization status persists Nx40 ms.
Here ‘N’ is decided by the REDDTH[7:0]
bits.
Less than 77 ’One’s are detected on the
Bit 2 of each channel during a 40 ms fixed
window and this status persists for Nx40
ms. Here ‘N’ is decided by the
YELDTH[7:0] bits.
More than 7 ‘0xFF00’ (MSB first) are
detected on the DL bits during a 40 ms
fixed window and this status persists for
Nx40 ms. Here ‘N’ is decided by the
YELDTH[7:0] bits.
Less than 4 ’One’s are detected on the Y
bit (Bit 6 in each CH 24) during a 40 ms
fixed window and this status persists for
Nx40 ms. Here ‘N’ is decided by the
YELDTH[7:0] bits.
Less than 4 zeros are detected on the F-
bit of the 12nd frame during a 40 ms fixed
window and this status persists for Nx40
ms. Here ‘N’ is decided by the
YELDTH[7:0] bits.
Less than 3 zeros are detected on the DL
bits during a 40 ms fixed window and this
status persists for Nx40 ms. Here ‘N’ is
decided by the YELDTH[7:0] bits.
Less than 61 zeros are detected in a 40
ms fixed window and this status persists
for Nx40 ms. Here ‘N’ is decided by the
AISDTH[7:0] bits.
Declare Condition
The in SF/ESF/T1 DM/SLC-96 syn-
chronization status persists Mx120 ms.
Here
REDCTH[7:0] bits.
More than 76 ’One’s are detected on
the Bit 2 of each channel during a 40
ms fixed window and this status per-
sists for Mx40 ms. Here ‘M’ is decided
by the YELCTH[7:0] bits.
Less than 8 ‘0xFF00’ (MSB first) are
detected on the DL bits during a 40 ms
fixed window and this status persists
for Mx40 ms. Here ‘M’ is decided by
the YELCTH[7:0] bits.
More than 3 ’One’s are detected on the
Y bit (Bit 6 in each CH 24) during a 40
ms fixed window and this status per-
sists for Mx40 ms. Here ‘M’ is decided
by the YELCTH[7:0] bits.
More than 3 zeros are detected on the
F-bit of the 12nd frame during a 40 ms
fixed window and this status persists
for Mx40 ms. Here ‘M’ is decided by
the YELCTH[7:0] bits.
More than 2 zeros are detected on the
DL bits during a 40 ms fixed window
and this status persists for Mx40 ms.
Here
YELCTH[7:0] bits.
More than 60 zeros are detected in a
40 ms fixed window and this status
persists for Mx40 ms. Here ‘M’ is
decided by the AISCTH[7:0] bits.
‘M’
‘M’
Clear Condition
is
is
58
decided
decided
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
cated by the corresponding Status bit. Any transition (from ‘0’ to ‘1’ or
from ‘1’ to ‘0’) on the Status bit will set the corresponding Interrupt Indi-
cation bit to ‘1’ and the Interrupt Indication bit will be cleared by writing a
‘1’. A ‘1’ in the Interrupt Indication bit means there is an interrupt. The
interrupt will be reported by the INT pin if its Interrupt Enable bit is ‘1’.
The status of the RED alarm, Yellow alarm and Blue alarm are indi-
by
by
the
the
Status
RED
YEL
YEL
YEL
YEL
YEL
AIS
Bit
Interrupt Indication
REDI
YELI
YELI
YELI
YELI
YELI
AISI
Bit
Interrupt Enable
March 04, 2009
REDE
YELE
YELE
YELE
YELE
YELE
AISE
Bit

Related parts for IDT82P2288BB