IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 28

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

the DPLL can be 6.77 Hz or 0.87 Hz, as selected by the RJA_BW bit.
The lower the CF is, the longer time is needed to achieve synchroniza-
tion.
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
RJA_IS bit. When the RJA_IS bit is ‘1’, an interrupt will be reported on
the INT pin if enabled by the RJA_IE bit.
by setting the RJA_LIMT bit. When the JA-Limit function is enabled, the
speed of the outgoing data will be adjusted automatically if the FIFO is
close to its full or emptiness. The criteria of speed adjustment start are
listed in Table 6. Though the JA-Limit function can reduce the possibility
of FIFO overflow and underflow, the quality of jitter attenuation is deteri-
orated.
Table 6: Criteria Of Speed Adjustment Start
read and write pointer of the FIFO or the peak-peak interval between the
read and write pointer of the FIFO can be indicated in the RJITT[6:0]
bits. When the RJITT_TEST bit is ‘0’, the current interval between the
Functional Description
IDT82P2288
If the incoming data moves faster than the outgoing data, the FIFO
To avoid overflow or underflow, the JA-Limit function can be enabled
Selected by the RJITT_TEST bit, the real time interval between the
FIFO Depth
128 bits
32 bits
64 bits
Criteria Of Speed Adjustment Start
2-bit close to full or empty
3-bit close to full or empty
4-bit close to full or empty
28
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
read and write pointer of the FIFO will be written into the RJITT[6:0] bits.
When the RJITT_TEST bit is ‘1’, the current interval will be compared
with the old one in the RJITT[6:0] bits and the larger one will be indi-
cated by the RJITT[6:0] bits.
G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/13,
AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.11 Jitter
Transfer for details.
Table 7: Related Bit / Register In Chapter 3.6
RJA_DP[1:0]
RJITT_TEST
RJA_LIMT
RJITT[6:0]
RJA_BW
The performance of Receive Jitter Attenuator meets the ITU-T I.431,
RJA_IS
RJA_IE
RJA_E
Bit
Receive Jitter Measure Value Indication
Receive Jitter Attenuation Configura-
Interrupt Enable Control 1
Interrupt Status 1
Register
tion
027, 127, 227, 327,
034, 134, 234, 334,
039, 139, 239, 339,
427, 527, 627, 727
434, 534, 634, 734
439, 539, 639, 739
March 04, 2009
Address (Hex)
03B, 13B, 23B,
33B, 43B, 53B,
63B, 73B