IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 85

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

bits and the TSOFF[6:0] bits are not ‘0’ respectively.
the corresponding frame input on the TSDn/MTSDA(MTSDB) pin will
delay ‘N’ clock cycles to the framing pulse on the TSFSn/MTSFS pin.
(Here ‘N’ is defined by the BOFF[2:0] bits.) When the CMS bit is ‘0’ and
the TSOFF[6:0] bits are set, the start of the corresponding frame input
on the TSDn/MTSDA(MTSDB) pin will delay ‘8 x M’ clock cycles to the
framing pulse on the TSFSn/MTSFS pin. (Here ‘M’ is defined by the
TSOFF[6:0].)
Functional Description
IDT82P2288
The bit offset and channel offset are configured when the BOFF[2:0]
When the CMS bit is ‘0’ and the BOFF[2:0] bits are set, the start of
Transmit Clock Master mode:
Transmit Clock Slave mode / Transmit Multiplexed mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSDA(B)
Figure 31. No Offset When FE = 1 & DE = 0 In Transmit Path
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
F-bit (T1/J1)
F-bit (T1/J1)
FE = 1, DE = 0
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OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
BOFF[2:0] bits are set, the start of the corresponding frame input on the
TSDn/MTSDA(MTSDB) pin will delay ‘2 x N’ clock cycles to the framing
pulse on the TSFSn/MTSFS pin. (Here ‘N’ is defined by the BOFF[2:0]
bits.) When the CMS bit is ‘1’ (i.e., in double clock mode) and the
TSOFF[6:0] bits are set, the start of the corresponding frame input on
the TSDn/MTSDA(MTSDB) pin will delay ‘16 x M’ clock cycles to the
framing pulse on the TSFSn/MTSFS pin. (Here ‘M’ is defined by the
TSOFF[6:0].)
0 to 23 channels (0 & 23 are included). In Multiplexed mode, the channel
offset can be configured from 0 to 127 channels (0 & 127 are included).
When the CMS bit is ‘1’ (i.e., in double clock mode) and the
In Non-multiplexed mode, the channel offset can be configured from
Bit 1 of CH1(T1/J1)
Bit 1 of CH1(T1/J1)
Bit 2 of TS0 (E1)
Bit 2 of TS0 (E1)
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
March 04, 2009