IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 68

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

3.16 RECEIVE PAYLOAD CONTROL
the received data stream can be extracted to the PRBS Generator/
Detector for test in this block.
bit must be set to ‘1’.
the RSDn/MRSDA(MRSDB) pins on a per-channel/per-TS basis or on a
global basis of the corresponding link (the methods are arranged from
the highest to the lowest in priority):
Functional Description
IDT82P2288
Different test patterns can be inserted in the received data stream or
To enable all the functions in the Receive Payload Control, the PCCE
The following methods can be executed on the data to be output on
• When the TESTEN bit is enabled and the PRBSDIR bit is ‘0’, the
received data will be extracted to the PRBS Generator/Detector.
The received data can be extracted in unframed mode, in 8-bit-
based mode or in 7-bit-based mode. This selection is made by the
PRBSMODE[1:0] bits. In unframed mode, all the received data
stream is extracted and the per-channel/per-TS configuration in
the TEST bit is ignored. In 8-bit-based mode or in 7-bit-based
mode, the received data will only be extracted on the channel/
timeslot configured by the TEST bit. Refer to Chapter 3.27.1 PRBS
Generator / Detector for details.
68
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
• Selected by the GSUBST[2:0] bits, the data of all channels/
• When the SIGFIX bit is set to ‘1’, the signaling bits (ABCD) will be
• Invert the most significant bit, the even bits and/or the odd bits by
• When the TESTEN bit is enabled and the PRBSDIR bit is ‘1’, the
timeslots of the corresponding link will be replaced by the data
trunk code set in the DTRK[7:0] bits, or the milliwatt pattern defined
in the Table 36 and Table 37. When the GSUBST[2:0] bits are set
to ‘000’, these replacements will be performed on a per-channel/
per-TS basis by setting the SUBST[2:0] bits in the corresponding
channel/timeslot.
fixed to the value set in the POL bit. This function is only supported
in the SF, ESF and SLC-96 formats in T1/J1 mode.
setting the SINV, OINV, EINV bits.
received data will be replaced by the test pattern generated from
the PRBS Generator/Detector. The received data can be replaced
in unframed mode, in 8-bit-based mode or in 7-bit-based mode.
This selection is made by the PRBSMODE[1:0] bits. In unframed
mode, all the received data stream is replaced and the per-chan-
nel/per-TS configuration in the TEST bit is ignored. In 8-bit-based
mode or in 7-bit-based mode, the received data will only be
replaced on the channel/timeslot configured by the TEST bit. Refer
to Chapter 3.27.1 PRBS Generator / Detector for details.
March 04, 2009