PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 133

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
2.7.4.1
Structure
The structure of the monitor channel is 8 bit wide, located at bit position 16-23 in every
time slot (assuming that the first bit in a time slot is located at bit position 0). Monitor
messages sent to the IPAC are 1 or 2 bytes long, monitor messages returned by the
IPAC are 0, 1, 2, or 5 bytes long depending on the command. Transmission of multiple
monitor bytes is specified by IOM-2. For handshake control in multiple byte transfers, bit
30, monitor read “MR”, and bit 31 monitor transmit “MX”, of every time slot are used.
Verification
A double last-look criterion is implemented for both bytes of the monitor message.
Codes
3 categories of monitor messages are supported by the IPAC:
• MON-1 S
• MON-2 S
• MON-8 Register access
The order of listing corresponds to the priority attributed to each category. MON-1
messages will be transmitted first, MON-8 messages last in case several messages are
initiated simultaneously.
The monitor channel is full duplex and operates on a pseudo-asynchronous basis, i.e.
while data transfer on the bus takes place synchronized to frame synchronization, the
flow of monitor data is controlled by the MR and MX bits. Monitor data will be transmitted
repeatedly until its reception is acknowledged.
Figure 65 illustrates a monitor transfer at maximum speed. The transmission of a 2-byte
monitor command followed by a 2-byte IPAC response requires a minimum of 12 IOM-
2 frames. In case the controller is able to confirm the receipt of first IPAC response byte
in the frame immediately following the MX transition on DOUT from HIGH to LOW (i.e.
in frame No. 6), 1 IOM frame may be saved.
Note:
Transmission and reception of monitor messages can be performed simultaneously by
the IPAC. This feature is used by the IPAC to send back the response before the
transmission from the controller is completed (IPAC does not wait for EOM from
controller).
M1/2: Monitor message 1. and 2. byte
Handshake Procedure
1
2
/Q channel
channel
133
Functional Description
PSB 2115
PSF 2115
11.97