PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 238

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

SIN ... Synchronous Transfer Interrupt
When programmed (STCR register), this interrupt is generated to enable the processor
to lock on to the IOM timing, for synchronous transfers.
TIN2 ... Timer Interrupt 2
The internal timer 2 counter has expired (see TIMR2 register).
Note: A read of the ISTAD register clears all bits except CIC. CIC is cleared by reading
4.3.4
Value after reset: 00
MASKD
Each interrupt source in the ISTAD register can be selectively masked by setting to “1”
the corresponding bit in MASKD. Masked interrupt status bits are not indicated when
ISTAD is read. Instead, they remain internally stored and pending, until the mask bit is
reset to “0”.
Note: In the event of a C/I channel change, CIC is set in ISTAD even if the corresponding
Semiconductor Group
CIR0.
mask bit in MASKD is active, but no interrupt is generated.
MASKD - Mask Register D-Channel (Write)
7
RME
RPF
H
(all interrupts enabled)
RSC
XPR
238
TIN
CIC
Detailed Register Description
SIN
0
TIN2
PSB 2115
PSF 2115
11.97
(A0)