PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 134

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

R1/2: Monitor response 1. and 2. byte
Figure 64
Idle State
After the bits MR and MX have been held inactive (i.e. HIGH) for two or more successive
IOM frames, the channel is considered idle in this direction.
Standard Transmission Procedure
1. The first byte of monitor data is placed by the external controller (e.g. ICC, EPIC) on
2. The IPAC reads the data of the monitor channel and acknowledges by setting the MR
3. The second byte of monitor data is placed by the controller on DU and the MX bit is set
4. The IPAC reads the new data byte in the monitor channel after the rising edge of MX
Semiconductor Group
the DU line of the IPAC and MX is activated (LOW; frame No 1).
bit of DD active if the transmitted bytes are identical in two received frames (frame No.
2 because the IPAC reads and compares data already while the MX bit is not
activated).
inactive for one single IOM frame. This is performed at a time convenient to the
controller.
has been detected. In the frame immediately following the MX transition active-to-
inactive, the MR bit of DD is set inactive. The MR transition inactive-to-active exactly
one IOM frame later is regarded as acknowledgment by the external controller (frame
No. 4-5).
IOM -2
DU
Mon.
DD
Mon. Data
R
Handshake Protocol with a 2-Byte Monitor Message/Response
Data
Frame
DU
DD
MX
MR
MX
MR
No.
1
0
1
0
1
0
1
0
T x 1.Byte
M1
FF
1
Ack.
M1
1.Byte
FF FF FF
2
M2
3
T x 2.Byte
M2
Ack. 2.Byte
4
134
T x 1.Byte
R1
FF
5
R1 R1
FF
6
Ack.
EOM
EOM
1.Byte
FF FF FF FF FF FF
7
T x 2.Byte
R2
8
R2
Ack. 2.Byte
9
10
FF
Functional Description
EOM
FF FF
11
ITD09644
EOM
12
PSB 2115
PSF 2115
11.97