PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 167

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Operational Description
3.3.2
D-Channel Interrupts
The cause of an interrupt related to the D-Channel is determined by the microprocessor
by reading the Interrupt Status Register ISTAD and the Extended Interrupt Status
Register EXIRD.
A read of the ISTAD register clears all bits except CIC. CIC is cleared by reading CIR0.
A read of EXIRD clears the EXD bit in ISTA as well as the EXIRD register itself.
Each interrupt source in ISTAD register can be selectively masked by setting to “1” the
corresponding bit in MASKD. Masked interrupt status bits are not indicated when ISTAD
is read. Instead, they remain internally stored and pending, until the mask bit is reset to
zero. Reading the ISTAD while a mask bit is active has no effect on the pending interrupt.
In the event of an extended interrupt EXIRD, EXD is not set when the corresponding
mask bit in MASK is active and no interrupt (INT) is generated. In the event of a C/I
channel interrupt CIC is set, even when the corresponding mask bit in MASKD is active,
but no interrupt (INT) is generated.
Except for CIC and MOS all interrupt sources are directly determined by a read of ISTAD
and EXIRD.
The FIFO logic, which consists of a 2 32 byte receive FIFO (RFIFOD) and a 2 32 byte
transmit FIFO (XFIFOD), as well as an intelligent FIFO controller, builds a flexible
interface to the upper protocol layers implemented in the microcontroller.
The interrupt sources from the D-Channel HDLC controller are listed in table 24.
Semiconductor Group
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