PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 200

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Operational Description
F6 synchronized
When the IPAC receives an activation signal (INFO 2), it responds with INFO 3 and waits
for normal frames (INFO 4).
F7 activated
This is the normal active state with the layer 1 protocol activated in both directions. From
state “F6 synchronized”, state F7 is reached almost 0.5 ms after reception of INFO 4.
F7 slip detected
When a slip is detected between the S/T-interface clocking system and the IOM-2
interface clocks (phase wander greater than 50 s, data may be disturbed, or 25 s if
programmed in the MON-8 Configuration Register) the IPAC enters this state,
synchronizing again the internal buffer. After 0.5 ms this state is left again (only possible
in LT-T mode).
Unconditional States TE/LT-T Mode
Loop A closed
On Activate Request Loop command, INFO 3 is sent by the line transmitter internally to
the line receiver (INFO0 is transmitted to the line). The receiver is not yet synchronized.
Loop A activated
The receiver is synchronized on INFO 3 which is looped back internally from the
transmitter. Data may be sent. The indication “AIL” is output to indicate the activated
state. When the S/T line awake detector, which is switched to the line, detects an
incoming signal, this is indicated by “RSY”.
Test mode 1
Single alternating pulses are sent on the S/T-interface (2 kHz repetition rate)
Test mode 2
Continuous alternating pulses are sent on the S/T-interface (96 kHz)
Semiconductor Group
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