PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 184

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Operational Description
The HDLC controller will request another data block by an XPR interrupt if there are no
more than 32 bytes in XFIFOD and the frame close command bit (Transmit Message
End XME) has not been set. To this the microcontroller responds by writing another pool
of data and re-issuing a transmit command for that pool. When XME is set, all remaining
bytes in XFIFOD are transmitted, the CRC field and the closing flag of the HDLC frame
are appended and the controller generates a new XPR interrupt.
The microcontroller does not necessarily have to transfer a frame in blocks of 32 bytes.
As a matter of fact, the sub-blocks issued by the microcontroller and separated by a
transmit command, can be between 0 and 32 bytes long.
If the XFIFOD runs out of data and the XME command bit has not been set, the frame
will be terminated with an abort sequence (seven 1’s) followed by inter-frame time fill,
and the microcontroller will be advised by a Transmit Data Underrun (XDU) interrupt. An
HDLC frame may also be aborted by setting the Transmitter Reset (XRES) command bit.
Semiconductor Group
184
11.97