PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 49

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

If the transmit pool is ready (which is true after an XPR interrupt or if the XFW bit in
STARD is set), the CPU can write a data block of up to 32 bytes to the transmit FIFO.
After this, data transmission can be initiated by command.
The transmission of transparent frames (command: XTF) and I frames (command: XIF)
is shown in figure 17.
Figure 17
2.2.1.3
A 2 32 byte FIFO buffer (transmit pools) is provided in the transmit direction.
Semiconductor Group
* Transmit
* Transmit
Transparent
Frame
I Frame
(auto-mode only!)
Transmitted
HDLC Frame
Transmission of Frames
Transmit Data Flow
Flag
Description of Symbols:
Address
XAD1
High
Generated automatically by IPAC
Written initially by CPU (into register)
Loaded (repeatedly) by CPU upon IPAC request (XPR interrupt)
Address
If 2 byte
address
field
selected
XAD2
Low
49
XFIFOD
Control
INFORMATION
XFIFOD
Functional Description
Appended if CPU
has issued
transmit message
end (XME)
command.
CRC
PSB 2115
PSF 2115
ITD09625
Flag
11.97