PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 56

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

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Semiconductor Group
5. After the transmission of an HDLC frame has been completed the D-Channel
2.3.4.2
The S-bus access procedure specified in ITU I.430 was defined to organize D-channel
access with multiple TEs connected to a single S-bus.
To implement collision detection the D (channel) and E (echo) bits are used. The D-
channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit (see
previous section).
The access to the D-channel is controlled by a priority mechanism which ensures that all
competing TEs are given a fair access chance. This priority mechanism discriminates
among the kind of information exchanged and information exchange history: Layer-2
frames are transmitted in such a way that signalling information is given priority (priority
class 1) over all other types of information exchange (priority class 2). Furthermore, once
a TE having successfully completed the transmission of a frame, it is assigned a lower
level of priority of that class. The TE is given back its normal level within a priority class
when all TEs have had an opportunity to transmit information at the normal level of that
priority class.
The priority mechanism is based on a rather simple method: A TE not transmitting layer-
2 frames sends binary 1s on the D-channel. As layer-2 frames are delimited by flags
consisting of the binary pattern “01111110” and zero bit insertion is used to prevent flag
imitation, the D-channel may be considered idle if more than seven consecutive 1s are
detected on the D-channel. Hence by monitoring the D echo channel, the TE may
determine if the D-channel is currently used by another TE or not.
A TE may start transmission of a layer-2 frame first when a certain number of
consecutive 1s has been received on the echo channel. This number is fixed to 8 in
priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower
level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and
11 for class 2.
A TE, when in the active condition, is monitoring the D echo channel, counting the
number of consecutive binary 1s. If a 0 bit is detected, the TE restarts counting the
number of consecutive binary 1s. If the required number of 1s according to the actual
through to the IOM-2 bus. The TIC bus request remains unaffected (i.e. if access was
granted the TIC address and BAC bit are activated). As soon as the S-bus D-channel
is clear and the S/G bit was set back to “GO” the controller will commence with data
transmission.
The S/G Bit generation in IOM-2 channel 2 is handled automatically by the IPAC
operating in TE mode.
controller withdraws from the TIC bus for two IOM-2 frames. This also applies when a
new HDLC frame is to be transmitted in immediate succession. With this mechanism
it is ensured that all connected controllers receive an equally fair chance to access the
TIC bus.
S-Bus Priority Mechanism for D-Channel
56
Functional Description
PSB 2115
PSF 2115
11.97