PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 192

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

It is essential to be able to interpret the state diagrams.
Figure 92
The following example illustrates the use of a state diagram with an extract of the TE
state diagram. The state explained is “F3 power down”.
The state may be entered by either of two methods:
– from state “test mode i” after the C/I command “DI” has been received.
– from state “F3 pending deactivation”, “F3 power up” or “F4 pending activation” after
The following informations are transmitted:
– INFO 0 (no signal) is sent on the S/T-interface.
– C/I message “DC” is issued on the IOM-2 interface.
The state may be left by either of the following methods:
– Leave for the state “F3 power up” after synchronous or asynchronous “TIM” code has
– Leave for state “F5/8 unsynchron” after any kind of signal (not INFO 0) has been
– Leave for state “F4 pending activation” in case C/I = AR8 or AR10 is received.
Semiconductor Group
the C/I command “DI” has been received.
been received on IOM.
recognized on the S/T-interface.
State Diagram Notation
INFO
S / T Interface
C /
IPAC
OUT
Ind.
i
x
State
192
Cmd.
IPAC
i
IN
r
Unconditional
Transition
Operational Description
ITD09657
PSB 2115
PSF 2115
11.97