PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 146

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.8.2
In LT-S and LT-T mode the IPAC provides a PCM interface (PCFG:PLD=0, default) that
can be disabled (PCFG:PLD=1), so that the PCM pins can be used as general I/O pins
(see previous chapter 2.8.1).
2.8.2.1
Through its standard PCM interface the IPAC can be connected to devices in general
TDM (time division multiplex) systems. In this way data controllers, which are not
IOM-2 compatible, can indirectly be connected to the IOM-2 interface, since the
programmed PCM timeslots are reflected in the corresponding IOM-2 B-channel
timeslots.
The data and signal lines to be used with the PCM interface depend on the mode of
operation and the type of interface of the external device:
Semiconductor Group
PCMIN
PCMOUT Transmit Data:
FSC
DCL
PCM Interface
PCM Lines
Receive Data:
The IPAC receives data from a peripheral device on PCMIN. The
received data is then mapped to a B-channel on the IOM-2 interface.
The IPAC transmits data to a peripheral device on PCMOUT. This data
is originated from a B-channel on the IOM-2 interface.
Frame Sync:
FSC is used on the IOM-2 interface to indicate the beginning of a new
IOM-2 frame. It is also used for the PCM interface to mark the
beginning of new frame.
Bit Clock (double rate):
DCL is the reference clock according to which data is written to
PCMOUT and read from PCMIN. For peripheral devices supporting
double rate bit clock, the clock signal is directly provided by SCLK (LT-
T mode) or by the system (LT-S mode).
DCL is the same clock as used for the IOM-2 interface.
146
Functional Description
PSB 2115
PSF 2115
11.97