PSB2115FV1.2D Lantiq, PSB2115FV1.2D Datasheet - Page 150

• Manufacturer Part Number: PSB2115FV1.2D
• Manufacturer: Lantiq

Specifications of PSB2115FV1.2D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 73
2.8.2.2
In LT-T mode a 1.536 MHz clock synchronous to the S interface is provided via pin
SCLK, which can be connected to the DCL input and used as the bit clock (double rate!)
for the IOM-2 interface. An internal divider derives from the DCL input either a common
FSC (division by 192) or a single bit clock (division by 2) which is suitable for external
devices that don’t support double rate (figure 74). The host can select whether FSC
(PCFG:FBS=0) or BCL (PCFG:FBS=1) is provided on FBOUT.
In LT-S mode the 1.536 MHz clock is to be provided by the system. In a similar way it
can be used as the DCL input for FSC/BCL generation.
Figure 74
Semiconductor Group
Clock Generation
BCL = 768 kHz
or
FSC = 8 kHz
DCL = 1.536 MHz
Data Path Switching
Generation of FSC and BCL in LT-T mode
*) Registers for timeslot
programming.
PCM
PCFG *)
PITA1/2
POTA1/2
PCM
TSAX *)
TSAR
XCCR
RCCR
FBOUT
SCLK (LT-T mode)
DCL
IOM-2
FIFO
Host
IOM
’1’
150
’0’
PCFG:FBS
PCFG:DPS
:192
:2
IPAC
2115_3
Functional Description
2115_0
PSB 2115
PSF 2115
11.97