T7115AMCD LSI, T7115AMCD Datasheet - Page 10

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Receive FIFO
Data received from the serial link interface is stored in
the 64-byte receive FIFO. In the HDLC mode, the
receiver also places a status of frame (SF) status byte
in the receiver FIFO for every completed frame
received. Whenever an SF frame status byte is present
in the receive FIFO, the EOF bit (R4—B7) is set. The
receiver queue status (RQS) bits (R4—B[6—0]) report
the number of bytes up to and including the first SF
frame status byte. If no SF frame status byte is present
in the FIFO (EOF, R4—B7 = 0), the count directly
reflects the number of data bytes available to be read.
Depending on frame size, it is possible for multiple
frames to be present in the FIFO. The receiver fill level
indicator (RIL) can be programmed in the receiver con-
trol register (R5—B[5—0]) to tailor the service time
interval to the system environment. The receiver full
(RF) interrupt bit is set in the interrupt status register
(R15—B3) when the FIFO reaches the prepro-
grammed full position. The RF interrupt condition is
reported in the interrupt register (R15—B3). If the RF
interrupt mask RFIE (R14—B3) is 1, the occurrence of
an RF interrupt condition causes a transition of the
interrupt pin if no other unmasked interrupts are
present. In dynamic interrupt mode (DINT,
R0—B0 = 1), this interrupt remains set until the condi-
tion is cleared. In nondynamic interrupt mode (DINT,
R0—B0 = 0), this interrupt is cleared by reading R15.
In the HDLC mode, an REOF interrupt is issued when
the receiver has identified the end of a frame and writ-
ten the SF status byte for that frame. An overrun inter-
rupt is generated when the receiver needs to write
either status or data to the FIFO and finds the FIFO full.
An overrun condition causes the last byte of the FIFO
to be overwritten with an SF status byte indicating the
overrun status. In the HDLC mode, an RIDL interrupt is
issued whenever 15 or more continuous 1s have been
received.
Block Move
The block-move mode is intended to support micropro-
cessors with a memory-to-memory move instruction.
Memory-to-memory move instructions can be faster
and reduce the amount of code needed to service the
FIFOs. Block-move mode allows the T7121 FIFOs to
appear as a block of memory. Systems using block
move need to allocate 16 addresses to the T7121 reg-
ister set (with AD6 = 0) and 64 addresses to the FIFOs
(with AD6 = 1). Block move is available only in the
MUXed address and data mode by setting the BM bit
in register 0 (R0—B3) to 1.
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10
(continued)
When block move is enabled (BM, R0—B3 = 1) and
AD6 is held high during the address cycle of the ALE,
the address is translated internally to R3, the data byte
register. All writes then go directly to the transmit FIFO,
and all reads address the receive FIFO. Normal regis-
ter addressing is accomplished by holding AD6 low
during the ALE address cycle. Block moves can be dis-
abled by clearing the BM bit (R0—B3) to 0.
Serial Link Interface
The HIFI-64 can interface to a wide variety of serial
links. In the simplest interface, the time-slot feature is
not used, and the HIFI-64 performs HDLC processing
in conjunction with three externally supplied clocks:
CLK, CLKR, and CLKX. The maximum data rate fre-
quency is 4.096 MHz, and the minimum CLK frequency
must be greater than two times the fastest data clock
frequency. In the case of a burst clock, the fastest data
clock frequency is defined as the clock frequency dur-
ing the burst.
If the time-slot feature is enabled (HWYEN,
R0—B7 = 1), the HIFI-64 is capable of controlling sep-
arate transmit and receive time slots on a wide variety
of time-division multiplexed (TDM) serial highways. In
particular, the HIFI-64 can interface to the Lucent Con-
centration Highway—a variable-speed, dual full-duplex
serial highway. The HIFI-64 can also interface to a vari-
ety of TDM highways containing 64 or fewer time slots
(primary-rate interface, SLD, K, K2, GCI, IOM, IOM2,
etc.).
The IOM, IOM2, and GCI interfaces specify the data
clock to be twice the data transmission frequency. In
order to comply with this specification, a Clock Mode
Select (CMS) bit (R8—B6) has been included. The bit
has the effect of dividing the data clock by two inter-
nally. In CMS mode, the minimum CLK frequency must
be greater than the data clock.
Enabling the Transmitter and Receiver
The HIFI-64 can transmit on either of two transmit data
pins (DXA, pin 19, and DXB, pin 17), or can broadcast
on both pins by appropriately programming the DXAC
(R7—B7) and DXBC (R7—B6) bits in the transmit time-
slot control register (R7—B6,B7). If both pins are
selected, the same data appears on both. The behavior
of pin 17, either DXB or
P17CTL (R5—B7) bit. The P17CTL bit must be cleared
to 0 to enable transmission on DXB. Pin 17 can be con-
figured as
is set to 1, the setting of DXBC (R7—B6) is ignored.
While configured as
HWYEN (R0—B7) = 0 and DXAC (R7—B7) = 1.
TSCA
by setting P17CTL to 1. When P17CTL
TSCA
TSCA
, pin 17 is low continually if
, is controlled by the
Lucent Technologies Inc.
Data Sheet
April 1997