T7115AMCD LSI, T7115AMCD Datasheet - Page 53

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Timing Characteristics
Separate Address and Data
Address on A3—A0, data on AD7—AD0.
Table 27. Separate Address and Data
* It is recommended that ALE be tied high when separate address and data bits are used. If ALE is pulled low, the T7121 enters multiplexed
† This is the time needed to update the receive FIFO status RQS (R4 B[6—0]).
address and data mode. ALE must then be held high for five master clock cycles, to switch back to separate address and data mode. ALE
must remain high during read and write operations.
Symbol on
Diagram
M
C
D
G
H
N
O
Q
A
B
E
F
K
P
J
L
I
tWRHWRL
tWRLWRH
tWRHCSH
tRDHCSH
tMCLMCL
tRWHALL
tCSLRWL
tRDLRDH
tRDHRDL
tALHCSL
tDVWRH
tWRHDI
tWRHAI
tRDLDV
tAVRDL
tRDHDI
tRDHAI
Name
ALE High to
RD
Address Valid to
Address Hold After
Address Hold After
Data Valid to
Data Hold After
CS
WR
RD
RD
RD
RD
WR
RD
Master Clock Period
WR
(minimum time between writes)
RD
(minimum time between reads);
Read R3 to Read R4
(continued)
Low to
or
Low to Data Valid (register 2 or 4)
Low to Data Valid (all others)
High to Data 3-state
Pulse Width
High to
High to
Pulse Width
High to
High to
WR
High to ALE Low*
RD
CS
RD
WR
CS
CS
WR
or
Parameter
High
Low
High
Low
WR
Low*
RD
WR
High
WR
RD
High
or
Low
†
WR
High
High
Low*
T7121 HDLC Interface for ISDN (HIFI-64)
1/2 tMCLMCL
tMCLMCL 40
5 tMCLMCL
2 tMCLMCL
4 tMCLMCL
83.3
Min
35
20
35
10
40
10
—
—
0
0
0
tMCLMCL + 40
<1/2 tDCLDCL
tMCLMCL
Max
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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