T7115AMCD LSI, T7115AMCD Datasheet - Page 42
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T7115AMCD
Manufacturer Part Number
T7115AMCD
Description
Manufacturer
LSI
Datasheet
1.T7115AMCD.pdf
(68 pages)
Specifications of T7115AMCD
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
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T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Table 22. Register R13—Transmitter Mask Register
Table 23. Alternate Register AR13—Transmitter Idle Character Register
42
AR13—B7
Register
Register
R13—B7
AR13
TBM7
TIC7
R13
(0)
(1)
B(0—7)
B(0—7)
AR13—B6
Bit
R13—B6
Bit
TBM6
TIC6
(0)
(1)
TIC0—TIC7
TBM0—TBM7 Transmitter Time-Slot Bit Mask. This register allows the HIFI-64 to
Symbol
Symbol
AR13—B5
R13—B5
(continued)
TBM5
TIC5
(0)
(1)
Transmitter Idle Character. This character is used only in transparent
mode (TRANS, R11—B6 = 1). When the pattern match bit (MATCH,
AR11—B5) is set to 1, the HIFI-64 transmits this character whenever the
transmit FIFO is empty. The default is to send the 1s idle character, but
any character can be programmed by the user.
transmit some subset of each byte during a time slot. A 1 in each bit
position instructs the HIFI-64 to send valid data during each bit time
when it is the HIFI-64's turn on the highway. Placing a 0 in any bit posi-
tion instructs the HIFI-64 to 3-state the transmit pin(s) during that bit
time. For example, 00000000 (default) means 3-state during the entire
time slot, 11000000 means transmit the two most significant bits dur-
ing each time slot, and 11111111 transmits the entire byte. See Fig-
ures 8 and 9 for examples of bit masking and subrate operation.
Default is all 0s so that the HIFI-64 does not transmit on the bus before
a time slot has been assigned.The masking feature is available only in
the TDM highway mode (i.e., HWYEN, R0—B7 = 1). TBM0 masks the
least significant bit transmitted (as defined by TLBIT, R10—B6).
AR13—B4
R13—B4
TBM4
TIC4
(0)
(1)
AR13—B3
R13—B3
TBM3
TIC3
(0)
(1)
Name/Function
Name/Function
AR13—B2
R13—B2
TBM2
TIC2
(0)
(1)
AR13—B1
R13—B1
Lucent Technologies Inc.
TBM1
TIC1
(0)
(1)
Data Sheet
April 1997
AR13—B0
R13—B0
TBM0
TIC0
(0)
(1)
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