T7115AMCD LSI, T7115AMCD Datasheet - Page 11

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Data Sheet
April 1997
Lucent Technologies Inc.
Functional Description
When HWYEN = 1 and DXAC = 1, pin 17
TSCA
The transmitter begins transmission when the transmitter enable ENT bit (R6—B3) is set to 1. Once the ENT bit is
enabled, user data is transmitted on the selected transmit data pin(s) (DXA, DXB, both, or neither). If the transmit-
ter is enabled and no transmit data pin has been selected, the HIFI-64 3-states both pins and the FIFO empties as
if the data were being transmitted. When the transmitter is disabled (ENT = 0), the transmitter continuously trans-
mits 1s on the selected transmit data pin(s) (DXA, DXB, or both). If neither DXA nor DXB is selected, both pins are
3-stated. The microprocessor can load the FIFO as normal while the transmitter is disabled. Disabling the transmit-
ter does not cause a transmitter reset. When the transmitter is disabled after having been enabled, the transmitter
should be reset via a TRES (R6—B5) = 1. Table 3 summarizes the transmit pin behavior based on the four register
bits that can affect it. This table assumes that P17CTL is set to 0 and that, in TDM highway modes, at least one
data bit is unmasked.
Table 3. Transmit Pin Behavior
* P17CTL = 0 is assumed.
The edge of CLKX (pin 18) used for data transmission is programmable by using CLKXI (R9—B4). Setting CLKXI
to 1 causes the T7121 to transmit data using the positive edge, while setting CLKXI to 0 enables transmission on
the negative edge (DEFAULT). Whenever the clock edge is changed, the transmitter should be reset via TRES
(R6—B5). When a gated clock is used to begin transmission on the first programmed clock edge, the opposite
clock edge must be provided first, after the reset. For example, if a gated clock with a negative edge transmission
is used, a positive edge of the clock should be provided first. This extra edge is only necessary on initial enabling of
the transmitter.
(R0—B7)
HWYEN
is high.
0
0
0
0
0
1
1
1
1
1
1
1
1
(R6—B3)
ENT
0
1
1
1
1
0
0
0
0
1
1
1
1
(R7—B7)
DXAC
X
0
0
1
1
0
0
1
1
0
0
1
1
(continued)
(R7—B6)
DXBC*
X
0
1
0
1
0
1
0
1
0
1
0
1
TSCA
is low during unmasked bits of the selected time slot. Otherwise
user data
user data
user data
user data
(Pin 19)
3-state
3-state
3-state
3-state
3-state
3-state
3-state
DXA
1s
1s
user data
user data
user data
user data
T7121 HDLC Interface for ISDN (HIFI-64)
(Pin 17)
3-state
3-state
3-state
3-state
3-state
3-state
3-state
DXB
1s
1s
Reset condition.
Data can be lost.
Concentration highway interface
enabled.
Transmit 1s during user-programmed
time slot until transmitter is enabled.
Data can be lost.
Comments
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